include: linux: Update kernel headers to version v5.19
Update kernel headers to v5.19 using utils/update-kernel-headers.sh and re-instating libcamera local modifications. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Jacopo Mondi <jacopo@jmondi.org> Tested-by: Jacopo Mondi <jacopo@jmondi.org>
This commit is contained in:
Laurent Pinchart
parent
2e77ccbb93
commit
37e85ff1dd
6 changed files with 418 additions and 23 deletions
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@ -1,4 +1,4 @@
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# SPDX-License-Identifier: CC0-1.0
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Files in this directory are imported from v5.16-rc7 of the Linux kernel. Do not
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Files in this directory are imported from v5.19 of the Linux kernel. Do not
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modify them manually.
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@ -92,7 +92,7 @@ struct dma_buf_sync {
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* between them in actual uapi, they're just different numbers.
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*/
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#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)
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#define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, u32)
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#define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, u64)
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#define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, __u32)
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#define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, __u64)
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#endif
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@ -314,6 +314,13 @@ extern "C" {
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/* 2 plane YCbCr420.
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* 3 10 bit components and 2 padding bits packed into 4 bytes.
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* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
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* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
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*/
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#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
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/* 3 plane non-subsampled (444) YCbCr
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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@ -630,6 +637,53 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
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/*
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* Intel Tile 4 layout
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*
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* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
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* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
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* only differs from Tile Y at the 256B granularity in between. At this
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* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
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* of 64B x 8 rows.
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*/
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#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
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/*
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* Intel color control surfaces (CCS) for DG2 render compression.
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*
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* The main surface is Tile 4 and at plane index 0. The CCS data is stored
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* outside of the GEM object in a reserved memory area dedicated for the
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* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
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* main surface pitch is required to be a multiple of four Tile 4 widths.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
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/*
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* Intel color control surfaces (CCS) for DG2 media compression.
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
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* pitch is required to be a multiple of four Tile 4 widths.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
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/*
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* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
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*
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* The main surface is Tile 4 and at plane index 0. The CCS data is stored
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* outside of the GEM object in a reserved memory area dedicated for the
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* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
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* main surface pitch is required to be a multiple of four Tile 4 widths. The
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* clear color is stored at plane index 1 and the pitch should be ignored. The
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* format of the 256 bits of clear color data matches the one used for the
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* I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
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* for details.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
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/*
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* IPU3 Bayer packing layout
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*
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@ -638,7 +692,7 @@ extern "C" {
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* the 6 most significant bits in the last byte unused. The format is little
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* endian.
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*/
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#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 9)
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#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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@ -677,6 +731,28 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
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/*
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* Qualcomm Tiled Format
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*
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* Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
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* Implementation may be platform and base-format specific.
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*
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* Each macrotile consists of m x n (mostly 4 x 4) tiles.
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* Pixel data pitch/stride is aligned with macrotile width.
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* Pixel data height is aligned with macrotile height.
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* Entire pixel data buffer is aligned with 4k(bytes).
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*/
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#define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
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/*
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* Qualcomm Alternate Tiled Format
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*
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* Alternate tiled format typically only used within GMEM.
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* Implementation may be platform and base-format specific.
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*/
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#define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
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/* Vivante framebuffer modifiers */
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/*
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@ -929,6 +1005,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* and UV. Some SAND-using hardware stores UV in a separate tiled
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* image from Y to reduce the column height, which is not supported
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* with these modifiers.
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*
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* The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
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* supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
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* wide, but as this is a 10 bpp format that translates to 96 pixels.
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*/
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#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
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@ -1439,11 +1519,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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#define AMD_FMT_MOD_PIPE_MASK 0x7
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#define AMD_FMT_MOD_SET(field, value) \
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((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
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((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
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#define AMD_FMT_MOD_GET(field, value) \
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(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
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#define AMD_FMT_MOD_CLEAR(field) \
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(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
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(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
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/* Mobile Industry Processor Interface (MIPI) modifiers */
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@ -34,11 +34,17 @@
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* struct ipu3_uapi_grid_config - Grid plane config
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*
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* @width: Grid horizontal dimensions, in number of grid blocks(cells).
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* For AWB, the range is (16, 80).
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* For AF/AE, the range is (16, 32).
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* @height: Grid vertical dimensions, in number of grid cells.
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* For AWB, the range is (16, 60).
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* For AF/AE, the range is (16, 24).
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* @block_width_log2: Log2 of the width of each cell in pixels.
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* for (2^3, 2^4, 2^5, 2^6, 2^7), values [3, 7].
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* For AWB, the range is [3, 6].
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* For AF/AE, the range is [3, 7].
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* @block_height_log2: Log2 of the height of each cell in pixels.
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* for (2^3, 2^4, 2^5, 2^6, 2^7), values [3, 7].
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* For AWB, the range is [3, 6].
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* For AF/AE, the range is [3, 7].
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* @height_per_slice: The number of blocks in vertical axis per slice.
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* Default 2.
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* @x_start: X value of top left corner of Region of Interest(ROI).
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@ -68,21 +74,21 @@ struct ipu3_uapi_grid_config {
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* @R_avg: Red average in the cell.
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* @B_avg: Blue average in the cell.
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* @Gb_avg: Green average for blue lines in the cell.
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* @sat_ratio: Percentage of pixels over a given threshold set in
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* @sat_ratio: Percentage of pixels over the thresholds specified in
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* ipu3_uapi_awb_config_s, coded from 0 to 255.
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* @padding0: Unused byte for padding.
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* @padding1: Unused byte for padding.
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* @padding2: Unused byte for padding.
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*/
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struct ipu3_uapi_awb_set_item {
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unsigned char Gr_avg;
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unsigned char R_avg;
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unsigned char B_avg;
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unsigned char Gb_avg;
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unsigned char sat_ratio;
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unsigned char padding0;
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unsigned char padding1;
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unsigned char padding2;
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__u8 Gr_avg;
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__u8 R_avg;
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__u8 B_avg;
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__u8 Gb_avg;
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__u8 sat_ratio;
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__u8 padding0;
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__u8 padding1;
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__u8 padding2;
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} __attribute__((packed));
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/*
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@ -98,7 +104,6 @@ struct ipu3_uapi_awb_set_item {
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(IPU3_UAPI_AWB_MAX_SETS * \
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(IPU3_UAPI_AWB_SET_SIZE + IPU3_UAPI_AWB_SPARE_FOR_BUBBLES))
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/**
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* struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
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*
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@ -128,6 +128,7 @@ enum v4l2_colorfx {
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V4L2_COLORFX_SOLARIZATION = 13,
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V4L2_COLORFX_ANTIQUE = 14,
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V4L2_COLORFX_SET_CBCR = 15,
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V4L2_COLORFX_SET_RGB = 16,
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};
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#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32)
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#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33)
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@ -145,9 +146,10 @@ enum v4l2_colorfx {
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#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41)
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#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42)
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#define V4L2_CID_COLORFX_RGB (V4L2_CID_BASE+43)
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/* last CID + 1 */
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#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43)
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#define V4L2_CID_LASTP1 (V4L2_CID_BASE+44)
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/* USER-class private control IDs */
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@ -221,6 +223,12 @@ enum v4l2_colorfx {
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*/
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#define V4L2_CID_USER_ALLEGRO_BASE (V4L2_CID_USER_BASE + 0x1170)
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/*
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* The base for the isl7998x driver controls.
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* We reserve 16 controls for this driver.
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*/
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#define V4L2_CID_USER_ISL7998X_BASE (V4L2_CID_USER_BASE + 0x1180)
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/* MPEG-class control IDs */
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/* The MPEG controls are applicable to all codec controls
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* and the 'MPEG' part of the define is historical */
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@ -443,6 +451,11 @@ enum v4l2_mpeg_video_multi_slice_mode {
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#define V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (V4L2_CID_CODEC_BASE+234)
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#define V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR (V4L2_CID_CODEC_BASE+235)
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#define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD (V4L2_CID_CODEC_BASE+236)
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#define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE (V4L2_CID_CODEC_BASE+237)
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enum v4l2_mpeg_video_intra_refresh_period_type {
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V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM = 0,
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V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC = 1,
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};
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/* CIDs for the MPEG-2 Part 2 (H.262) codec */
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#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_CODEC_BASE+270)
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@ -1563,6 +1576,8 @@ struct v4l2_h264_dpb_entry {
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#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01
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#define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC 0x02
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#define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD 0x04
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#define V4L2_H264_DECODE_PARAM_FLAG_PFRAME 0x08
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#define V4L2_H264_DECODE_PARAM_FLAG_BFRAME 0x10
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#define V4L2_CID_STATELESS_H264_DECODE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 7)
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/**
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@ -2018,6 +2033,290 @@ struct v4l2_ctrl_hdr10_mastering_display {
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__u32 min_display_mastering_luminance;
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};
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/* Stateless VP9 controls */
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#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1
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#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2
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/**
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* struct v4l2_vp9_loop_filter - VP9 loop filter parameters
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*
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* @ref_deltas: contains the adjustment needed for the filter level based on the
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* chosen reference frame. If this syntax element is not present in the bitstream,
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* users should pass its last value.
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* @mode_deltas: contains the adjustment needed for the filter level based on the
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* chosen mode. If this syntax element is not present in the bitstream, users should
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* pass its last value.
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* @level: indicates the loop filter strength.
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* @sharpness: indicates the sharpness level.
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* @flags: combination of V4L2_VP9_LOOP_FILTER_FLAG_{} flags.
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* @reserved: padding field. Should be zeroed by applications.
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*
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* This structure contains all loop filter related parameters. See sections
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* '7.2.8 Loop filter semantics' of the VP9 specification for more details.
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*/
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struct v4l2_vp9_loop_filter {
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__s8 ref_deltas[4];
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__s8 mode_deltas[2];
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__u8 level;
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__u8 sharpness;
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__u8 flags;
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__u8 reserved[7];
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};
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/**
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* struct v4l2_vp9_quantization - VP9 quantization parameters
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*
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* @base_q_idx: indicates the base frame qindex.
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* @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx.
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* @delta_q_uv_dc: indicates the UV DC quantizer relative to base_q_idx.
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* @delta_q_uv_ac: indicates the UV AC quantizer relative to base_q_idx.
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* @reserved: padding field. Should be zeroed by applications.
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*
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* Encodes the quantization parameters. See section '7.2.9 Quantization params
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* syntax' of the VP9 specification for more details.
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*/
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struct v4l2_vp9_quantization {
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__u8 base_q_idx;
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__s8 delta_q_y_dc;
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__s8 delta_q_uv_dc;
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__s8 delta_q_uv_ac;
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__u8 reserved[4];
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};
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#define V4L2_VP9_SEGMENTATION_FLAG_ENABLED 0x01
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#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP 0x02
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#define V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE 0x04
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#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA 0x08
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#define V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE 0x10
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#define V4L2_VP9_SEG_LVL_ALT_Q 0
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#define V4L2_VP9_SEG_LVL_ALT_L 1
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#define V4L2_VP9_SEG_LVL_REF_FRAME 2
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#define V4L2_VP9_SEG_LVL_SKIP 3
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#define V4L2_VP9_SEG_LVL_MAX 4
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#define V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) (1 << (id))
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#define V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK 0xf
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/**
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* struct v4l2_vp9_segmentation - VP9 segmentation parameters
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*
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* @feature_data: data attached to each feature. Data entry is only valid if
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* the feature is enabled. The array shall be indexed with segment number as
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* the first dimension (0..7) and one of V4L2_VP9_SEG_{} as the second dimension.
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* @feature_enabled: bitmask defining which features are enabled in each segment.
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* The value for each segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id)
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* values where id is one of V4L2_VP9_SEG_LVL_{}.
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* @tree_probs: specifies the probability values to be used when decoding a
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* Segment-ID. See '5.15. Segmentation map' section of the VP9 specification
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* for more details.
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* @pred_probs: specifies the probability values to be used when decoding a
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* Predicted-Segment-ID. See '6.4.14. Get segment id syntax' section of :ref:`vp9`
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* for more details.
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* @flags: combination of V4L2_VP9_SEGMENTATION_FLAG_{} flags.
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* @reserved: padding field. Should be zeroed by applications.
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*
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* Encodes the quantization parameters. See section '7.2.10 Segmentation params syntax' of
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* the VP9 specification for more details.
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*/
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struct v4l2_vp9_segmentation {
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__s16 feature_data[8][4];
|
||||
__u8 feature_enabled[8];
|
||||
__u8 tree_probs[7];
|
||||
__u8 pred_probs[3];
|
||||
__u8 flags;
|
||||
__u8 reserved[5];
|
||||
};
|
||||
|
||||
#define V4L2_VP9_FRAME_FLAG_KEY_FRAME 0x001
|
||||
#define V4L2_VP9_FRAME_FLAG_SHOW_FRAME 0x002
|
||||
#define V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT 0x004
|
||||
#define V4L2_VP9_FRAME_FLAG_INTRA_ONLY 0x008
|
||||
#define V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV 0x010
|
||||
#define V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX 0x020
|
||||
#define V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE 0x040
|
||||
#define V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING 0x080
|
||||
#define V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING 0x100
|
||||
#define V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING 0x200
|
||||
|
||||
#define V4L2_VP9_SIGN_BIAS_LAST 0x1
|
||||
#define V4L2_VP9_SIGN_BIAS_GOLDEN 0x2
|
||||
#define V4L2_VP9_SIGN_BIAS_ALT 0x4
|
||||
|
||||
#define V4L2_VP9_RESET_FRAME_CTX_NONE 0
|
||||
#define V4L2_VP9_RESET_FRAME_CTX_SPEC 1
|
||||
#define V4L2_VP9_RESET_FRAME_CTX_ALL 2
|
||||
|
||||
#define V4L2_VP9_INTERP_FILTER_EIGHTTAP 0
|
||||
#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH 1
|
||||
#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP 2
|
||||
#define V4L2_VP9_INTERP_FILTER_BILINEAR 3
|
||||
#define V4L2_VP9_INTERP_FILTER_SWITCHABLE 4
|
||||
|
||||
#define V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE 0
|
||||
#define V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE 1
|
||||
#define V4L2_VP9_REFERENCE_MODE_SELECT 2
|
||||
|
||||
#define V4L2_VP9_PROFILE_MAX 3
|
||||
|
||||
#define V4L2_CID_STATELESS_VP9_FRAME (V4L2_CID_CODEC_STATELESS_BASE + 300)
|
||||
/**
|
||||
* struct v4l2_ctrl_vp9_frame - VP9 frame decoding control
|
||||
*
|
||||
* @lf: loop filter parameters. See &v4l2_vp9_loop_filter for more details.
|
||||
* @quant: quantization parameters. See &v4l2_vp9_quantization for more details.
|
||||
* @seg: segmentation parameters. See &v4l2_vp9_segmentation for more details.
|
||||
* @flags: combination of V4L2_VP9_FRAME_FLAG_{} flags.
|
||||
* @compressed_header_size: compressed header size in bytes.
|
||||
* @uncompressed_header_size: uncompressed header size in bytes.
|
||||
* @frame_width_minus_1: add 1 to it and you'll get the frame width expressed in pixels.
|
||||
* @frame_height_minus_1: add 1 to it and you'll get the frame height expressed in pixels.
|
||||
* @render_width_minus_1: add 1 to it and you'll get the expected render width expressed in
|
||||
* pixels. This is not used during the decoding process but might be used by HW scalers
|
||||
* to prepare a frame that's ready for scanout.
|
||||
* @render_height_minus_1: add 1 to it and you'll get the expected render height expressed in
|
||||
* pixels. This is not used during the decoding process but might be used by HW scalers
|
||||
* to prepare a frame that's ready for scanout.
|
||||
* @last_frame_ts: "last" reference buffer timestamp.
|
||||
* The timestamp refers to the timestamp field in struct v4l2_buffer.
|
||||
* Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.
|
||||
* @golden_frame_ts: "golden" reference buffer timestamp.
|
||||
* The timestamp refers to the timestamp field in struct v4l2_buffer.
|
||||
* Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.
|
||||
* @alt_frame_ts: "alt" reference buffer timestamp.
|
||||
* The timestamp refers to the timestamp field in struct v4l2_buffer.
|
||||
* Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.
|
||||
* @ref_frame_sign_bias: a bitfield specifying whether the sign bias is set for a given
|
||||
* reference frame. Either of V4L2_VP9_SIGN_BIAS_{}.
|
||||
* @reset_frame_context: specifies whether the frame context should be reset to default values.
|
||||
* Either of V4L2_VP9_RESET_FRAME_CTX_{}.
|
||||
* @frame_context_idx: frame context that should be used/updated.
|
||||
* @profile: VP9 profile. Can be 0, 1, 2 or 3.
|
||||
* @bit_depth: bits per components. Can be 8, 10 or 12. Note that not all profiles support
|
||||
* 10 and/or 12 bits depths.
|
||||
* @interpolation_filter: specifies the filter selection used for performing inter prediction.
|
||||
* Set to one of V4L2_VP9_INTERP_FILTER_{}.
|
||||
* @tile_cols_log2: specifies the base 2 logarithm of the width of each tile (where the width
|
||||
* is measured in units of 8x8 blocks). Shall be less than or equal to 6.
|
||||
* @tile_rows_log2: specifies the base 2 logarithm of the height of each tile (where the height
|
||||
* is measured in units of 8x8 blocks).
|
||||
* @reference_mode: specifies the type of inter prediction to be used.
|
||||
* Set to one of V4L2_VP9_REFERENCE_MODE_{}.
|
||||
* @reserved: padding field. Should be zeroed by applications.
|
||||
*/
|
||||
struct v4l2_ctrl_vp9_frame {
|
||||
struct v4l2_vp9_loop_filter lf;
|
||||
struct v4l2_vp9_quantization quant;
|
||||
struct v4l2_vp9_segmentation seg;
|
||||
__u32 flags;
|
||||
__u16 compressed_header_size;
|
||||
__u16 uncompressed_header_size;
|
||||
__u16 frame_width_minus_1;
|
||||
__u16 frame_height_minus_1;
|
||||
__u16 render_width_minus_1;
|
||||
__u16 render_height_minus_1;
|
||||
__u64 last_frame_ts;
|
||||
__u64 golden_frame_ts;
|
||||
__u64 alt_frame_ts;
|
||||
__u8 ref_frame_sign_bias;
|
||||
__u8 reset_frame_context;
|
||||
__u8 frame_context_idx;
|
||||
__u8 profile;
|
||||
__u8 bit_depth;
|
||||
__u8 interpolation_filter;
|
||||
__u8 tile_cols_log2;
|
||||
__u8 tile_rows_log2;
|
||||
__u8 reference_mode;
|
||||
__u8 reserved[7];
|
||||
};
|
||||
|
||||
#define V4L2_VP9_NUM_FRAME_CTX 4
|
||||
|
||||
/**
|
||||
* struct v4l2_vp9_mv_probs - VP9 Motion vector probability updates
|
||||
* @joint: motion vector joint probability updates.
|
||||
* @sign: motion vector sign probability updates.
|
||||
* @classes: motion vector class probability updates.
|
||||
* @class0_bit: motion vector class0 bit probability updates.
|
||||
* @bits: motion vector bits probability updates.
|
||||
* @class0_fr: motion vector class0 fractional bit probability updates.
|
||||
* @fr: motion vector fractional bit probability updates.
|
||||
* @class0_hp: motion vector class0 high precision fractional bit probability updates.
|
||||
* @hp: motion vector high precision fractional bit probability updates.
|
||||
*
|
||||
* This structure contains new values of motion vector probabilities.
|
||||
* A value of zero in an array element means there is no update of the relevant probability.
|
||||
* See `struct v4l2_vp9_prob_updates` for details.
|
||||
*/
|
||||
struct v4l2_vp9_mv_probs {
|
||||
__u8 joint[3];
|
||||
__u8 sign[2];
|
||||
__u8 classes[2][10];
|
||||
__u8 class0_bit[2];
|
||||
__u8 bits[2][10];
|
||||
__u8 class0_fr[2][2][3];
|
||||
__u8 fr[2][3];
|
||||
__u8 class0_hp[2];
|
||||
__u8 hp[2];
|
||||
};
|
||||
|
||||
#define V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (V4L2_CID_CODEC_STATELESS_BASE + 301)
|
||||
|
||||
#define V4L2_VP9_TX_MODE_ONLY_4X4 0
|
||||
#define V4L2_VP9_TX_MODE_ALLOW_8X8 1
|
||||
#define V4L2_VP9_TX_MODE_ALLOW_16X16 2
|
||||
#define V4L2_VP9_TX_MODE_ALLOW_32X32 3
|
||||
#define V4L2_VP9_TX_MODE_SELECT 4
|
||||
|
||||
/**
|
||||
* struct v4l2_ctrl_vp9_compressed_hdr - VP9 probability updates control
|
||||
* @tx_mode: specifies the TX mode. Set to one of V4L2_VP9_TX_MODE_{}.
|
||||
* @tx8: TX 8x8 probability updates.
|
||||
* @tx16: TX 16x16 probability updates.
|
||||
* @tx32: TX 32x32 probability updates.
|
||||
* @coef: coefficient probability updates.
|
||||
* @skip: skip probability updates.
|
||||
* @inter_mode: inter mode probability updates.
|
||||
* @interp_filter: interpolation filter probability updates.
|
||||
* @is_inter: is inter-block probability updates.
|
||||
* @comp_mode: compound prediction mode probability updates.
|
||||
* @single_ref: single ref probability updates.
|
||||
* @comp_ref: compound ref probability updates.
|
||||
* @y_mode: Y prediction mode probability updates.
|
||||
* @uv_mode: UV prediction mode probability updates.
|
||||
* @partition: partition probability updates.
|
||||
* @mv: motion vector probability updates.
|
||||
*
|
||||
* This structure holds the probabilities update as parsed in the compressed
|
||||
* header (Spec 6.3). These values represent the value of probability update after
|
||||
* being translated with inv_map_table[] (see 6.3.5). A value of zero in an array element
|
||||
* means that there is no update of the relevant probability.
|
||||
*
|
||||
* This control is optional and needs to be used when dealing with the hardware which is
|
||||
* not capable of parsing the compressed header itself. Only drivers which need it will
|
||||
* implement it.
|
||||
*/
|
||||
struct v4l2_ctrl_vp9_compressed_hdr {
|
||||
__u8 tx_mode;
|
||||
__u8 tx8[2][1];
|
||||
__u8 tx16[2][2];
|
||||
__u8 tx32[2][3];
|
||||
__u8 coef[4][2][2][6][6][3];
|
||||
__u8 skip[3];
|
||||
__u8 inter_mode[7][3];
|
||||
__u8 interp_filter[4][2];
|
||||
__u8 is_inter[4];
|
||||
__u8 comp_mode[5];
|
||||
__u8 single_ref[5][2];
|
||||
__u8 comp_ref[5];
|
||||
__u8 y_mode[4][9];
|
||||
__u8 uv_mode[10][9];
|
||||
__u8 partition[16][3];
|
||||
|
||||
struct v4l2_vp9_mv_probs mv;
|
||||
};
|
||||
|
||||
/* MPEG-compression definitions kept for backwards compatibility */
|
||||
#define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC
|
||||
#define V4L2_CID_MPEG_CLASS V4L2_CID_CODEC_CLASS
|
||||
|
|
|
|||
|
|
@ -563,6 +563,7 @@ struct v4l2_pix_format {
|
|||
/* Grey bit-packed formats */
|
||||
#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */
|
||||
#define V4L2_PIX_FMT_Y10P v4l2_fourcc('Y', '1', '0', 'P') /* 10 Greyscale, MIPI RAW10 packed */
|
||||
#define V4L2_PIX_FMT_IPU3_Y10 v4l2_fourcc('i', 'p', '3', 'y') /* IPU3 packed 10-bit greyscale */
|
||||
|
||||
/* Palette formats */
|
||||
#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
|
||||
|
|
@ -626,6 +627,8 @@ struct v4l2_pix_format {
|
|||
/* Tiled YUV formats, non contiguous planes */
|
||||
#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 tiles */
|
||||
#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 tiles */
|
||||
#define V4L2_PIX_FMT_NV12M_8L128 v4l2_fourcc('N', 'A', '1', '2') /* Y/CbCr 4:2:0 8x128 tiles */
|
||||
#define V4L2_PIX_FMT_NV12M_10BE_8L128 v4l2_fourcc_be('N', 'T', '1', '2') /* Y/CbCr 4:2:0 10-bit 8x128 tiles */
|
||||
|
||||
/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */
|
||||
#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */
|
||||
|
|
@ -697,6 +700,7 @@ struct v4l2_pix_format {
|
|||
#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
|
||||
#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 parsed frame */
|
||||
#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */
|
||||
#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') /* VP9 parsed frame */
|
||||
#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */
|
||||
#define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */
|
||||
#define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */
|
||||
|
|
@ -737,8 +741,10 @@ struct v4l2_pix_format {
|
|||
#define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */
|
||||
#define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */
|
||||
#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* BTTV 8-bit dithered RGB */
|
||||
#define V4L2_PIX_FMT_QC08C v4l2_fourcc('Q', '0', '8', 'C') /* Qualcomm 8-bit compressed */
|
||||
#define V4L2_PIX_FMT_QC10C v4l2_fourcc('Q', '1', '0', 'C') /* Qualcomm 10-bit compressed */
|
||||
|
||||
/* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */
|
||||
/* 10bit raw packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */
|
||||
#define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */
|
||||
#define V4L2_PIX_FMT_IPU3_SGBRG10 v4l2_fourcc('i', 'p', '3', 'g') /* IPU3 packed 10-bit GBRG bayer */
|
||||
#define V4L2_PIX_FMT_IPU3_SGRBG10 v4l2_fourcc('i', 'p', '3', 'G') /* IPU3 packed 10-bit GRBG bayer */
|
||||
|
|
@ -1732,6 +1738,8 @@ struct v4l2_ext_control {
|
|||
struct v4l2_ctrl_mpeg2_sequence *p_mpeg2_sequence;
|
||||
struct v4l2_ctrl_mpeg2_picture *p_mpeg2_picture;
|
||||
struct v4l2_ctrl_mpeg2_quantisation *p_mpeg2_quantisation;
|
||||
struct v4l2_ctrl_vp9_compressed_hdr *p_vp9_compressed_hdr_probs;
|
||||
struct v4l2_ctrl_vp9_frame *p_vp9_frame;
|
||||
void *ptr;
|
||||
};
|
||||
} __attribute__ ((packed));
|
||||
|
|
@ -1792,6 +1800,9 @@ enum v4l2_ctrl_type {
|
|||
V4L2_CTRL_TYPE_MPEG2_QUANTISATION = 0x0250,
|
||||
V4L2_CTRL_TYPE_MPEG2_SEQUENCE = 0x0251,
|
||||
V4L2_CTRL_TYPE_MPEG2_PICTURE = 0x0252,
|
||||
|
||||
V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR = 0x0260,
|
||||
V4L2_CTRL_TYPE_VP9_FRAME = 0x0261,
|
||||
};
|
||||
|
||||
/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue