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https://gitlab.alpinelinux.org/alpine/aports.git
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89 lines
2 KiB
Diff
89 lines
2 KiB
Diff
From 90050202f57b22243f5d3dd434a81df2f89de9ed Mon Sep 17 00:00:00 2001
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From: Quentin Carbonneaux
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Date: Tue, 1 Oct 2024 19:38:15 +0200
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Subject: fix various codegen bugs on arm64
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- dynamic allocations could generate
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bad 'and' instructions (for the
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and with -16 in salloc()).
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- symbols used in w context would
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generate adrp and add instructions
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on wN registers while they seem to
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only work on xN registers.
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Thanks to Rosie for reporting them.
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---
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arm64/emit.c | 19 ++++++++++++++-----
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test/isel5.ssa | 16 ++++++++++++++++
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2 files changed, 30 insertions(+), 5 deletions(-)
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create mode 100644 test/isel5.ssa
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diff --git a/arm64/emit.c b/arm64/emit.c
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index ffdc178..28cd6a5 100644
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--- a/arm64/emit.c
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+++ b/arm64/emit.c
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@@ -160,7 +160,8 @@ emitf(char *s, Ins *i, E *e)
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Ref r;
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int k, c;
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Con *pc;
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- uint n, sp;
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+ uint64_t n;
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+ uint sp;
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fputc('\t', e->f);
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@@ -217,10 +218,17 @@ emitf(char *s, Ins *i, E *e)
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pc = &e->fn->con[r.val];
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n = pc->bits.i;
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assert(pc->type == CBits);
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- if (n & 0xfff000)
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- fprintf(e->f, "#%u, lsl #12", n>>12);
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- else
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- fprintf(e->f, "#%u", n);
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+ if (n >> 24) {
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+ assert(arm64_logimm(n, k));
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+ fprintf(e->f, "#%"PRIu64, n);
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+ } else if (n & 0xfff000) {
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+ assert(!(n & ~0xfff000ull));
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+ fprintf(e->f, "#%"PRIu64", lsl #12",
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+ n>>12);
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+ } else {
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+ assert(!(n & ~0xfffull));
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+ fprintf(e->f, "#%"PRIu64, n);
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+ }
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break;
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}
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break;
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@@ -304,6 +312,7 @@ loadcon(Con *c, int r, int k, E *e)
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rn = rname(r, k);
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n = c->bits.i;
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if (c->type == CAddr) {
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+ rn = rname(r, Kl);
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loadaddr(c, rn, e);
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return;
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}
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diff --git a/test/isel5.ssa b/test/isel5.ssa
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new file mode 100644
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index 0000000..9c546d7
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--- /dev/null
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+++ b/test/isel5.ssa
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@@ -0,0 +1,16 @@
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+# make sure the local symbols used for
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+# fp constants do not get a _ prefix
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+# on apple arm hardware
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+
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+export function w $main() {
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+@start
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+ %r =d copy d_1.2
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+ %x =w call $printf(l $fmt, ..., d %r)
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+ ret 0
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+}
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+
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+data $fmt = { b "%.06f\n", b 0 }
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+
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+# >>> output
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+# 1.200000
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+# <<<
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--
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cgit v1.2.3
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