Mirror/betaflight
1
0
Fork 0
mirror of https://github.com/betaflight/betaflight.git synced 2025-07-21 07:15:18 +03:00
Code Issues Wiki Activity

Added TIM_UP + burst DMA -based DSHOT to F3

Browse source
This commit is contained in:
DieHertz 2017-12-27 01:05:09 +03:00 • committed by Andrey Mironov
parent 2207a98a7a
commit a89409a26a
5 changed files with 47 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/main/drivers/pwm_output.h
View file

@ -111,7 +111,11 @@ typedef struct {
TIM_TypeDef *timer; TIM_TypeDef *timer;
#if defined(USE_DSHOT_DMAR) #if defined(USE_DSHOT_DMAR)
#if !defined(USE_HAL_DRIVER) #if !defined(USE_HAL_DRIVER)
#ifdef STM32F3
DMA_Channel_TypeDef *dmaBurstRef;
#else
DMA_Stream_TypeDef *dmaBurstRef; DMA_Stream_TypeDef *dmaBurstRef;
#endif
uint16_t dmaBurstLength; uint16_t dmaBurstLength;
#endif #endif
uint32_t dmaBurstBuffer[DSHOT_DMA_BUFFER_SIZE * 4]; uint32_t dmaBurstBuffer[DSHOT_DMA_BUFFER_SIZE * 4];

19
src/main/drivers/pwm_output_dshot.c
View file

@ -119,16 +119,16 @@ static void motor_DMA_IRQHandler(dmaChannelDescriptor_t *descriptor)
void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output)
{ {
#if defined(STM32F3) #if defined(STM32F4) || defined(STM32F7)
DMA_Channel_TypeDef *dmaRef = timerHardware->dmaRef; typedef DMA_Stream_TypeDef dmaStream_t;
#elif defined(STM32F4)
#ifdef USE_DSHOT_DMAR
DMA_Stream_TypeDef *dmaRef = timerHardware->dmaTimUPRef;
#else #else
DMA_Stream_TypeDef *dmaRef = timerHardware->dmaRef; typedef DMA_Channel_TypeDef dmaStream_t;
#endif #endif
#ifdef USE_DSHOT_DMAR
dmaStream_t *dmaRef = timerHardware->dmaTimUPRef;
#else #else
#error "No MCU specified in DSHOT" dmaStream_t *dmaRef = timerHardware->dmaRef;
#endif #endif
if (dmaRef == NULL) { if (dmaRef == NULL) {
@ -213,6 +213,10 @@ void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m
dmaInit(timerHardware->dmaTimUPIrqHandler, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim)); dmaInit(timerHardware->dmaTimUPIrqHandler, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim));
dmaSetHandler(timerHardware->dmaTimUPIrqHandler, motor_DMA_IRQHandler, NVIC_BUILD_PRIORITY(1, 2), motorIndex); dmaSetHandler(timerHardware->dmaTimUPIrqHandler, motor_DMA_IRQHandler, NVIC_BUILD_PRIORITY(1, 2), motorIndex);
#if defined(STM32F3)
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)motor->timer->dmaBurstBuffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
#else
DMA_InitStructure.DMA_Channel = timerHardware->dmaTimUPChannel; DMA_InitStructure.DMA_Channel = timerHardware->dmaTimUPChannel;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)motor->timer->dmaBurstBuffer; DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)motor->timer->dmaBurstBuffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
@ -220,6 +224,7 @@ void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
#endif
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&timerHardware->tim->DMAR; DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&timerHardware->tim->DMAR;
DMA_InitStructure.DMA_BufferSize = (pwmProtocolType == PWM_TYPE_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX DMA_InitStructure.DMA_BufferSize = (pwmProtocolType == PWM_TYPE_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;

8
src/main/drivers/timer.h
View file

@ -100,14 +100,18 @@ typedef struct timerHardware_s {
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
DMA_Stream_TypeDef *dmaRef; DMA_Stream_TypeDef *dmaRef;
uint32_t dmaChannel; uint32_t dmaChannel;
#elif defined(STM32F3) || defined(STM32F1) #else
DMA_Channel_TypeDef *dmaRef; DMA_Channel_TypeDef *dmaRef;
#endif #endif
uint8_t dmaIrqHandler; uint8_t dmaIrqHandler;
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F3) || defined(STM32F4) || defined(STM32F7)
// TIMUP // TIMUP
#ifdef STM32F3
DMA_Channel_TypeDef *dmaTimUPRef;
#else
DMA_Stream_TypeDef *dmaTimUPRef; DMA_Stream_TypeDef *dmaTimUPRef;
uint32_t dmaTimUPChannel; uint32_t dmaTimUPChannel;
#endif
uint8_t dmaTimUPIrqHandler; uint8_t dmaTimUPIrqHandler;
#endif #endif
#endif #endif

33
src/main/drivers/timer_def.h
View file

@ -171,6 +171,10 @@
DEF_TIM_DMA_COND( \ DEF_TIM_DMA_COND( \
DEF_TIM_DMA_CHANNEL(TCH_## tim ## _ ## chan), \ DEF_TIM_DMA_CHANNEL(TCH_## tim ## _ ## chan), \
DEF_TIM_DMA_HANDLER(TCH_## tim ## _ ## chan) \ DEF_TIM_DMA_HANDLER(TCH_## tim ## _ ## chan) \
), \
DEF_TIM_DMA_COND( \
DEF_TIM_DMA_CHANNEL(TCH_## tim ## _UP), \
DEF_TIM_DMA_HANDLER(TCH_## tim ## _UP) \
) \ ) \
} \ } \
/**/ /**/
@ -198,11 +202,9 @@
#define DEF_TIM_DMA__BTCH_TIM1_CH4 D(1, 4) #define DEF_TIM_DMA__BTCH_TIM1_CH4 D(1, 4)
#define DEF_TIM_DMA__BTCH_TIM1_TRIG D(1, 4) #define DEF_TIM_DMA__BTCH_TIM1_TRIG D(1, 4)
#define DEF_TIM_DMA__BTCH_TIM1_COM D(1, 4) #define DEF_TIM_DMA__BTCH_TIM1_COM D(1, 4)
#define DEF_TIM_DMA__BTCH_TIM1_UP D(1, 5)
#define DEF_TIM_DMA__BTCH_TIM1_CH3 D(1, 6) #define DEF_TIM_DMA__BTCH_TIM1_CH3 D(1, 6)
#define DEF_TIM_DMA__BTCH_TIM2_CH3 D(1, 1) #define DEF_TIM_DMA__BTCH_TIM2_CH3 D(1, 1)
#define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 2)
#define DEF_TIM_DMA__BTCH_TIM2_CH1 D(1, 5) #define DEF_TIM_DMA__BTCH_TIM2_CH1 D(1, 5)
#define DEF_TIM_DMA__BTCH_TIM2_CH2 D(1, 7) #define DEF_TIM_DMA__BTCH_TIM2_CH2 D(1, 7)
#define DEF_TIM_DMA__BTCH_TIM2_CH4 D(1, 7) #define DEF_TIM_DMA__BTCH_TIM2_CH4 D(1, 7)
@ -210,14 +212,12 @@
#define DEF_TIM_DMA__BTCH_TIM3_CH2 NONE #define DEF_TIM_DMA__BTCH_TIM3_CH2 NONE
#define DEF_TIM_DMA__BTCH_TIM3_CH3 D(1, 2) #define DEF_TIM_DMA__BTCH_TIM3_CH3 D(1, 2)
#define DEF_TIM_DMA__BTCH_TIM3_CH4 D(1, 3) #define DEF_TIM_DMA__BTCH_TIM3_CH4 D(1, 3)
#define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 3)
#define DEF_TIM_DMA__BTCH_TIM3_CH1 D(1, 6) #define DEF_TIM_DMA__BTCH_TIM3_CH1 D(1, 6)
#define DEF_TIM_DMA__BTCH_TIM3_TRIG D(1, 6) #define DEF_TIM_DMA__BTCH_TIM3_TRIG D(1, 6)
#define DEF_TIM_DMA__BTCH_TIM4_CH1 D(1, 1) #define DEF_TIM_DMA__BTCH_TIM4_CH1 D(1, 1)
#define DEF_TIM_DMA__BTCH_TIM4_CH2 D(1, 4) #define DEF_TIM_DMA__BTCH_TIM4_CH2 D(1, 4)
#define DEF_TIM_DMA__BTCH_TIM4_CH3 D(1, 5) #define DEF_TIM_DMA__BTCH_TIM4_CH3 D(1, 5)
#define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 7)
#define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE #define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE
#define DEF_TIM_DMA__BTCH_TIM15_CH1 D(1, 5) #define DEF_TIM_DMA__BTCH_TIM15_CH1 D(1, 5)
@ -228,28 +228,43 @@
#ifdef REMAP_TIM16_DMA #ifdef REMAP_TIM16_DMA
#define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 6) #define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 6)
#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 6)
#else #else
#define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 3) #define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 3)
#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 3)
#endif #endif
#ifdef REMAP_TIM17_DMA #ifdef REMAP_TIM17_DMA
#define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 7) #define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 7)
#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 7)
#else #else
#define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 1) #define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 1)
#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 1)
#endif #endif
#define DEF_TIM_DMA__BTCH_TIM8_CH3 D(2, 1) #define DEF_TIM_DMA__BTCH_TIM8_CH3 D(2, 1)
#define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1)
#define DEF_TIM_DMA__BTCH_TIM8_CH4 D(2, 2) #define DEF_TIM_DMA__BTCH_TIM8_CH4 D(2, 2)
#define DEF_TIM_DMA__BTCH_TIM8_TRIG D(2, 2) #define DEF_TIM_DMA__BTCH_TIM8_TRIG D(2, 2)
#define DEF_TIM_DMA__BTCH_TIM8_COM D(2, 2) #define DEF_TIM_DMA__BTCH_TIM8_COM D(2, 2)
#define DEF_TIM_DMA__BTCH_TIM8_CH1 D(2, 3) #define DEF_TIM_DMA__BTCH_TIM8_CH1 D(2, 3)
#define DEF_TIM_DMA__BTCH_TIM8_CH2 D(2, 5) #define DEF_TIM_DMA__BTCH_TIM8_CH2 D(2, 5)
// TIM_UP table
#define DEF_TIM_DMA__BTCH_TIM1_UP D(1, 5)
#define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 2)
#define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 3)
#define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 7)
#define DEF_TIM_DMA__BTCH_TIM6_UP D(2, 3)
#define DEF_TIM_DMA__BTCH_TIM7_UP D(2, 4)
#define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1)
#define DEF_TIM_DMA__BTCH_TIM15_UP D(1, 5)
#ifdef REMAP_TIM16_DMA
#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 6)
#else
#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 3)
#endif
#ifdef REMAP_TIM17_DMA
#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 7)
#else
#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 1)
#endif
// AF table // AF table
#define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1) #define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1)

1
src/main/target/common_fc_pre.h
View file

@ -41,6 +41,7 @@
#ifdef STM32F3 #ifdef STM32F3
#define MINIMAL_CLI #define MINIMAL_CLI
#define USE_DSHOT #define USE_DSHOT
#define USE_DSHOT_DMAR
#define USE_GYRO_DATA_ANALYSE #define USE_GYRO_DATA_ANALYSE
#endif #endif