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https://github.com/betaflight/betaflight.git
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Added TIM_UP + burst DMA -based DSHOT to F3
This commit is contained in:
DieHertz
Andrey Mironov
parent
2207a98a7a
commit
a89409a26a
5 changed files with 47 additions and 18 deletions
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@ -111,7 +111,11 @@ typedef struct {
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TIM_TypeDef *timer;
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#if defined(USE_DSHOT_DMAR)
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#if !defined(USE_HAL_DRIVER)
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#ifdef STM32F3
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DMA_Channel_TypeDef *dmaBurstRef;
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#else
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DMA_Stream_TypeDef *dmaBurstRef;
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#endif
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uint16_t dmaBurstLength;
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#endif
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uint32_t dmaBurstBuffer[DSHOT_DMA_BUFFER_SIZE * 4];
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@ -119,16 +119,16 @@ static void motor_DMA_IRQHandler(dmaChannelDescriptor_t *descriptor)
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void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output)
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{
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#if defined(STM32F3)
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DMA_Channel_TypeDef *dmaRef = timerHardware->dmaRef;
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#elif defined(STM32F4)
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#ifdef USE_DSHOT_DMAR
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DMA_Stream_TypeDef *dmaRef = timerHardware->dmaTimUPRef;
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#if defined(STM32F4) || defined(STM32F7)
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typedef DMA_Stream_TypeDef dmaStream_t;
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#else
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DMA_Stream_TypeDef *dmaRef = timerHardware->dmaRef;
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typedef DMA_Channel_TypeDef dmaStream_t;
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#endif
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#ifdef USE_DSHOT_DMAR
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dmaStream_t *dmaRef = timerHardware->dmaTimUPRef;
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#else
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#error "No MCU specified in DSHOT"
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dmaStream_t *dmaRef = timerHardware->dmaRef;
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#endif
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if (dmaRef == NULL) {
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@ -213,6 +213,10 @@ void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m
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dmaInit(timerHardware->dmaTimUPIrqHandler, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim));
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dmaSetHandler(timerHardware->dmaTimUPIrqHandler, motor_DMA_IRQHandler, NVIC_BUILD_PRIORITY(1, 2), motorIndex);
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#if defined(STM32F3)
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)motor->timer->dmaBurstBuffer;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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#else
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DMA_InitStructure.DMA_Channel = timerHardware->dmaTimUPChannel;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)motor->timer->dmaBurstBuffer;
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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@ -220,6 +224,7 @@ void pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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#endif
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&timerHardware->tim->DMAR;
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DMA_InitStructure.DMA_BufferSize = (pwmProtocolType == PWM_TYPE_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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@ -100,14 +100,18 @@ typedef struct timerHardware_s {
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#if defined(STM32F4) || defined(STM32F7)
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DMA_Stream_TypeDef *dmaRef;
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uint32_t dmaChannel;
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#elif defined(STM32F3) || defined(STM32F1)
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#else
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DMA_Channel_TypeDef *dmaRef;
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#endif
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uint8_t dmaIrqHandler;
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#if defined(STM32F4) || defined(STM32F7)
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#if defined(STM32F3) || defined(STM32F4) || defined(STM32F7)
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// TIMUP
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#ifdef STM32F3
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DMA_Channel_TypeDef *dmaTimUPRef;
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#else
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DMA_Stream_TypeDef *dmaTimUPRef;
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uint32_t dmaTimUPChannel;
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#endif
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uint8_t dmaTimUPIrqHandler;
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#endif
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#endif
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@ -171,6 +171,10 @@
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DEF_TIM_DMA_COND( \
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DEF_TIM_DMA_CHANNEL(TCH_## tim ## _ ## chan), \
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DEF_TIM_DMA_HANDLER(TCH_## tim ## _ ## chan) \
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), \
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DEF_TIM_DMA_COND( \
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DEF_TIM_DMA_CHANNEL(TCH_## tim ## _UP), \
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DEF_TIM_DMA_HANDLER(TCH_## tim ## _UP) \
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) \
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} \
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/**/
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@ -198,11 +202,9 @@
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#define DEF_TIM_DMA__BTCH_TIM1_CH4 D(1, 4)
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#define DEF_TIM_DMA__BTCH_TIM1_TRIG D(1, 4)
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#define DEF_TIM_DMA__BTCH_TIM1_COM D(1, 4)
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#define DEF_TIM_DMA__BTCH_TIM1_UP D(1, 5)
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#define DEF_TIM_DMA__BTCH_TIM1_CH3 D(1, 6)
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#define DEF_TIM_DMA__BTCH_TIM2_CH3 D(1, 1)
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#define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 2)
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#define DEF_TIM_DMA__BTCH_TIM2_CH1 D(1, 5)
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#define DEF_TIM_DMA__BTCH_TIM2_CH2 D(1, 7)
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#define DEF_TIM_DMA__BTCH_TIM2_CH4 D(1, 7)
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@ -210,14 +212,12 @@
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#define DEF_TIM_DMA__BTCH_TIM3_CH2 NONE
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#define DEF_TIM_DMA__BTCH_TIM3_CH3 D(1, 2)
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#define DEF_TIM_DMA__BTCH_TIM3_CH4 D(1, 3)
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#define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 3)
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#define DEF_TIM_DMA__BTCH_TIM3_CH1 D(1, 6)
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#define DEF_TIM_DMA__BTCH_TIM3_TRIG D(1, 6)
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#define DEF_TIM_DMA__BTCH_TIM4_CH1 D(1, 1)
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#define DEF_TIM_DMA__BTCH_TIM4_CH2 D(1, 4)
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#define DEF_TIM_DMA__BTCH_TIM4_CH3 D(1, 5)
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#define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 7)
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#define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE
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#define DEF_TIM_DMA__BTCH_TIM15_CH1 D(1, 5)
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@ -228,28 +228,43 @@
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#ifdef REMAP_TIM16_DMA
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#define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 6)
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#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 6)
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#else
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#define DEF_TIM_DMA__BTCH_TIM16_CH1 D(1, 3)
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#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 3)
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#endif
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#ifdef REMAP_TIM17_DMA
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#define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 7)
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#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 7)
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#else
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#define DEF_TIM_DMA__BTCH_TIM17_CH1 D(1, 1)
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#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 1)
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#endif
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#define DEF_TIM_DMA__BTCH_TIM8_CH3 D(2, 1)
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#define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1)
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#define DEF_TIM_DMA__BTCH_TIM8_CH4 D(2, 2)
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#define DEF_TIM_DMA__BTCH_TIM8_TRIG D(2, 2)
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#define DEF_TIM_DMA__BTCH_TIM8_COM D(2, 2)
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#define DEF_TIM_DMA__BTCH_TIM8_CH1 D(2, 3)
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#define DEF_TIM_DMA__BTCH_TIM8_CH2 D(2, 5)
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// TIM_UP table
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#define DEF_TIM_DMA__BTCH_TIM1_UP D(1, 5)
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#define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 2)
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#define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 3)
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#define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 7)
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#define DEF_TIM_DMA__BTCH_TIM6_UP D(2, 3)
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#define DEF_TIM_DMA__BTCH_TIM7_UP D(2, 4)
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#define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1)
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#define DEF_TIM_DMA__BTCH_TIM15_UP D(1, 5)
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#ifdef REMAP_TIM16_DMA
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#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 6)
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#else
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#define DEF_TIM_DMA__BTCH_TIM16_UP D(1, 3)
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#endif
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#ifdef REMAP_TIM17_DMA
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#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 7)
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#else
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#define DEF_TIM_DMA__BTCH_TIM17_UP D(1, 1)
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#endif
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// AF table
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#define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1)
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@ -41,6 +41,7 @@
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#ifdef STM32F3
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#define MINIMAL_CLI
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#define USE_DSHOT
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#define USE_DSHOT_DMAR
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#define USE_GYRO_DATA_ANALYSE
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#endif
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