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[G4] Add I2C pins overloaded with SWD pins

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This commit is contained in:
jflyper 2020-06-22 01:34:28 +09:00
parent b1a3699753
commit be3b321d7a
1 changed files with 11 additions and 3 deletions
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14
src/main/drivers/bus_i2c_hal_init.c
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@ -149,8 +149,12 @@ const i2cHardware_t i2cHardware[I2CDEV_COUNT] = {
{
.device = I2CDEV_1,
.reg = I2C1,
.sclPins = { I2CPINDEF(PA15, GPIO_AF4_I2C1), I2CPINDEF(PB6, GPIO_AF4_I2C1), I2CPINDEF(PB8, GPIO_AF4_I2C1), },
.sdaPins = { I2CPINDEF(PB7, GPIO_AF4_I2C1), I2CPINDEF(PB9, GPIO_AF4_I2C1), },
// Some boards are overloading SWD pins with I2C1 for maximum pin utilization on 48-pin CE(U) packages.
// Be carefull when using SWD on these boards if I2C1 pins are defined by default.
.sclPins = { I2CPINDEF(PA13, GPIO_AF4_I2C1), I2CPINDEF(PA15, GPIO_AF4_I2C1), I2CPINDEF(PB6, GPIO_AF4_I2C1), I2CPINDEF(PB8, GPIO_AF4_I2C1), },
.sdaPins = { I2CPINDEF(PA14, GPIO_AF4_I2C1), I2CPINDEF(PB7, GPIO_AF4_I2C1), I2CPINDEF(PB9, GPIO_AF4_I2C1), },
.rcc = RCC_APB11(I2C1),
.ev_irq = I2C1_EV_IRQn,
.er_irq = I2C1_ER_IRQn,
@ -182,7 +186,11 @@ const i2cHardware_t i2cHardware[I2CDEV_COUNT] = {
{
.device = I2CDEV_4,
.reg = I2C4,
.sclPins = { I2CPINDEF(PB6, GPIO_AF3_I2C4), I2CPINDEF(PC6, GPIO_AF8_I2C4), },
// Here, SWDIO(PA13) is overloaded with I2C4_SCL, too.
// See comment in the I2C1 section above.
.sclPins = { I2CPINDEF(PA13, GPIO_AF3_I2C4), I2CPINDEF(PB6, GPIO_AF3_I2C4), I2CPINDEF(PC6, GPIO_AF8_I2C4), },
.sdaPins = { I2CPINDEF(PB7, GPIO_AF4_I2C4), I2CPINDEF(PC7, GPIO_AF8_I2C4), },
.rcc = RCC_APB12(I2C4),
.ev_irq = I2C4_EV_IRQn,