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Fix timerUpConfig initialization and TIMER_INDEX macro usage
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c6ba65dfd8
commit
c9640b3387
4 changed files with 38 additions and 32 deletions
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@ -5425,10 +5425,9 @@ static void printPeripheralDmaoptDetails(dmaoptEntry_t *entry, int index, const
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int uiIndex;
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if (entry->presenceMask) {
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if (!(BIT(index + 1) & entry->presenceMask)) {
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uiIndex = timerGetNumberByIndex(index);
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if (!(BIT(uiIndex) & entry->presenceMask))
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return;
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}
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uiIndex = index + 1;
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} else {
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uiIndex = DMA_OPT_UI_INDEX(index);
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}
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@ -29,49 +29,56 @@
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#include "timerup.h"
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#define TIM_N(n) (1 << (n))
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#define TIMER_INDEX(i) BITCOUNT((TIM_N(i) - 1) & USED_TIMERS)
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PG_REGISTER_ARRAY_WITH_RESET_FN(timerUpConfig_t, HARDWARE_TIMER_DEFINITION_COUNT, timerUpConfig, PG_TIMER_UP_CONFIG, 0);
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void pgResetFn_timerUpConfig(timerUpConfig_t *config)
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{
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for (unsigned timno = 0; timno < HARDWARE_TIMER_DEFINITION_COUNT; timno++) {
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config[timno].dmaopt = DMA_OPT_UNUSED;
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timerUpConfig_t cfg[HARDWARE_TIMER_DEFINITION_COUNT];
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for (int i = 0; i < HARDWARE_TIMER_DEFINITION_COUNT; i++) {
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cfg[i].dmaopt = DMA_OPT_UNUSED;
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}
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#if defined(TIMUP1_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 0) && (TIMUP_TIMERS & BIT(1))
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config[0].dmaopt = TIMUP1_DMA_OPT;
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#if defined(TIMUP1_DMA_OPT) && (TIMUP_TIMERS & BIT(1))
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cfg[TIMER_INDEX(1)].dmaopt = TIMUP1_DMA_OPT;
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#endif
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#if defined(TIMUP2_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 1) && (TIMUP_TIMERS & BIT(2))
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config[1].dmaopt = TIMUP2_DMA_OPT;
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#if defined(TIMUP2_DMA_OPT) && (TIMUP_TIMERS & BIT(2))
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cfg[TIMER_INDEX(2)].dmaopt = TIMUP2_DMA_OPT;
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#endif
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#if defined(TIMUP3_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 2) && (TIMUP_TIMERS & BIT(3))
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config[2].dmaopt = TIMUP3_DMA_OPT;
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#if defined(TIMUP3_DMA_OPT) && (TIMUP_TIMERS & BIT(3))
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cfg[TIMER_INDEX(3)].dmaopt = TIMUP3_DMA_OPT;
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#endif
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#if defined(TIMUP4_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 3) && (TIMUP_TIMERS & BIT(4))
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config[3].dmaopt = TIMUP4_DMA_OPT;
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#if defined(TIMUP4_DMA_OPT) && (TIMUP_TIMERS & BIT(4))
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cfg[TIMER_INDEX(4)].dmaopt = TIMUP4_DMA_OPT;
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#endif
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#if defined(TIMUP5_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 4) && (TIMUP_TIMERS & BIT(5))
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config[4].dmaopt = TIMUP5_DMA_OPT;
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#if defined(TIMUP5_DMA_OPT) && (TIMUP_TIMERS & BIT(5))
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cfg[TIMER_INDEX(5)].dmaopt = TIMUP5_DMA_OPT;
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#endif
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#if defined(TIMUP6_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 5) && (TIMUP_TIMERS & BIT(6))
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config[5].dmaopt = TIMUP6_DMA_OPT;
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#if defined(TIMUP6_DMA_OPT) && (TIMUP_TIMERS & BIT(6))
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cfg[TIMER_INDEX(6)].dmaopt = TIMUP6_DMA_OPT;
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#endif
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#if defined(TIMUP7_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 6) && (TIMUP_TIMERS & BIT(7))
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config[6].dmaopt = TIMUP7_DMA_OPT;
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#if defined(TIMUP7_DMA_OPT) && (TIMUP_TIMERS & BIT(7))
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cfg[TIMER_INDEX(7)].dmaopt = TIMUP7_DMA_OPT;
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#endif
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#if defined(TIMUP8_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 7) && (TIMUP_TIMERS & BIT(8))
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config[7].dmaopt = TIMUP8_DMA_OPT;
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#if defined(TIMUP8_DMA_OPT) && (TIMUP_TIMERS & BIT(8))
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cfg[TIMER_INDEX(8)].dmaopt = TIMUP8_DMA_OPT;
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#endif
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#if defined(TIMUP15_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 14) && (TIMUP_TIMERS & BIT(15))
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config[14].dmaopt = TIMUP15_DMA_OPT;
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#if defined(TIMUP15_DMA_OPT) && (TIMUP_TIMERS & BIT(15))
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cfg[TIMER_INDEX(15)].dmaopt = TIMUP15_DMA_OPT;
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#endif
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#if defined(TIMUP16_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 15) && (TIMUP_TIMERS & BIT(16))
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config[15].dmaopt = TIMUP16_DMA_OPT;
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#if defined(TIMUP16_DMA_OPT) && (TIMUP_TIMERS & BIT(16))
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cfg[TIMER_INDEX(16)].dmaopt = TIMUP16_DMA_OPT;
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#endif
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#if defined(TIMUP17_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 16) && (TIMUP_TIMERS & BIT(17))
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config[16].dmaopt = TIMUP17_DMA_OPT;
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#if defined(TIMUP17_DMA_OPT) && (TIMUP_TIMERS & BIT(17))
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cfg[TIMER_INDEX(17)].dmaopt = TIMUP17_DMA_OPT;
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#endif
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#if defined(TIMUP20_DMA_OPT) && (HARDWARE_TIMER_DEFINITION_COUNT > 19) && (TIMUP_TIMERS & BIT(20))
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config[19].dmaopt = TIMUP20_DMA_OPT;
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#if defined(TIMUP20_DMA_OPT) && (TIMUP_TIMERS & BIT(20))
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cfg[TIMER_INDEX(20)].dmaopt = TIMUP20_DMA_OPT;
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#endif
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memcpy(config, cfg, HARDWARE_TIMER_DEFINITION_COUNT);
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}
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#endif
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@ -27,7 +27,7 @@
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#define USED_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(20) )
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#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(20) )
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#define FULL_TIMER_CHANNEL_COUNT 109
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#define HARDWARE_TIMER_DEFINITION_COUNT 15
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#define HARDWARE_TIMER_DEFINITION_COUNT 13
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// allow conditional definition of DMA related members
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#if defined(USE_TIMER_DMA)
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@ -1149,14 +1149,14 @@
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#define FULL_TIMER_CHANNEL_COUNT 91
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#define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(12) | TIM_N(13) | TIM_N(14) | TIM_N(15) | TIM_N(16) | TIM_N(17) )
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#define HARDWARE_TIMER_DEFINITION_COUNT 17
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#define HARDWARE_TIMER_DEFINITION_COUNT 14
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#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) )
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#elif defined(STM32G4)
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#define FULL_TIMER_CHANNEL_COUNT 93 // XXX Need review
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#define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(15) | TIM_N(16) | TIM_N(17) | TIM_N(20) )
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#define HARDWARE_TIMER_DEFINITION_COUNT 20
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#define HARDWARE_TIMER_DEFINITION_COUNT 12
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#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) | BIT(20))
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#endif
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