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define PLL setting for overclock
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parent
0a7a74965a
commit
f47b438918
3 changed files with 10 additions and 5 deletions
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@ -268,11 +268,11 @@ void init(void)
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#if defined(STM32F4) && !defined(DISABLE_OVERCLOCK)
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// If F4 Overclocking is set and System core clock is not correct a reset is forced
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if (systemConfig()->cpu_overclock && SystemCoreClock != 240000000) {
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if (systemConfig()->cpu_overclock && SystemCoreClock != OC_FREQUENCY_HZ) {
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*((uint32_t *)0x2001FFF8) = 0xBABEFACE; // 128KB SRAM STM32F4XX
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__disable_irq();
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NVIC_SystemReset();
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} else if (!systemConfig()->cpu_overclock && SystemCoreClock == 240000000) {
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} else if (!systemConfig()->cpu_overclock && SystemCoreClock == OC_FREQUENCY_HZ) {
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*((uint32_t *)0x2001FFF8) = 0x0; // 128KB SRAM STM32F4XX
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__disable_irq();
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NVIC_SystemReset();
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@ -505,9 +505,9 @@ void SystemInit(void)
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void SystemInitOC(void)
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{
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/* PLL setting for overclocking */
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pll_n = 480;
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pll_p = 2;
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pll_q = 10;
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pll_n = PLL_N_OC;
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pll_p = PLL_P_OC;
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pll_q = PLL_Q_OC;
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SystemInit();
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}
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@ -32,6 +32,11 @@
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extern "C" {
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#endif
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#define PLL_N_OC 480
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#define PLL_P_OC 2
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#define PLL_Q_OC 10
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#define OC_FREQUENCY_HZ PLL_N_OC/PLL_P_OC*1000000
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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extern void SystemInit(void);
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extern void SystemInitOC(void);
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