jflyper
d4cfff2e9d
Use unified clock specs, remove per target specs.
2018-09-21 22:40:02 +09:00
jflyper
6402ebf5b8
Increase SPI_PREINIT_IPU_COUNT
2018-05-30 01:50:54 +09:00
jflyper
f9a43099db
SPI CS preinit for configurability
2018-05-24 22:00:26 +09:00
blckmn
a9f74cd6df
Removed excess trailing spaces before new lines on licenses.
2018-04-25 20:58:00 +10:00
blckmn
46fe22b4bd
Direct license replacement
2018-04-22 09:22:46 +10:00
Dominic Clifton
cde9a9517b
SPRacingF7DUAL - Dual SIMULTANEOUS gyro support. ( #5264 )
...
* CF/BF - Set STM32F7 SPI FAST clock to 13.5Mhz - Gyros not stable at
27mhz.
* CF/BF - Initial SPRacingF7DUAL commit.
Support two simultaneous gyro support (code by Dominic Clifton and Martin Budden)
There are new debug modes so you can see the difference between each gyro.
Notes:
* spi bus instance caching broke spi mpu detection because the detection
tries I2C first which overwrites the selected bus instance when using
dual gyro.
* ALL other dual-gyro boards have one sensor per bus. SPRacingF7DUAL is has two per bus and thus commit has a lot of changes to fix SPI/BUS/GYRO initialisation issues.
* CF/BF - Add SPRacingF4EVODG target.
This target adds a second gyro to the board using the SPI pads on the back of the board.
* CF/BF - Temporarily disable Gyro EXTI pin to allow NEO target to build.
2018-03-04 11:29:31 +13:00
mikeller
09d396c05c
Cleaned up parameter group handling.
...
Fixed missing include.
2017-12-31 10:51:01 +13:00
mikeller
b38738894c
Moved bus_spi parameter group to pg/.
2017-12-25 07:24:32 +13:00
jflyper
cc573574b2
Preinit for MAX7456 on Kakute F4 requires output hi.
2017-09-25 21:07:32 +09:00
blckmn
834289e456
Move all F7 to use LL
2017-07-30 12:10:46 +10:00
Martin Budden
2fd20c2bd9
Rename SPI functions. Rationalise parameter order.
2017-07-20 16:22:59 +01:00
jflyper
d2c71a6f7e
Add bus parameters to barometerConfig_t, cli handling
2017-07-16 23:57:16 +09:00
jflyper
815dd0a188
Doh!!!
2017-07-11 18:32:05 +09:00
jflyper
f9f4b4263c
Make names more clear
2017-07-11 15:12:13 +09:00
jflyper
a864b869ae
Call transmit buffer out and receive buffer in
2017-07-11 09:44:13 +09:00
Martin Budden
b78a8bd519
Improved efficiency of gyro read for SPI
2017-07-02 05:32:18 +01:00
jflyper
d18a06f721
Merge remote-tracking branch 'betaflight/master' into bfdev-configurable-spi-phase-1
2017-07-02 11:06:50 +09:00
Martin Budden
6edb4b9c19
Cache SPI handle to improve performance
2017-07-01 20:39:38 +01:00
Martin Budden
6157ebe5e3
Removed abbreviations from SPI read/write functions
2017-07-01 16:28:10 +01:00
Martin Budden
5d7f8cdd6e
Function renaming as per ledvinap's suggestion
2017-07-01 16:28:10 +01:00
Martin Budden
8df87bc47d
Make SPI read and write register generic
2017-07-01 16:28:09 +01:00
jflyper
ac668e2c6d
Merge branch 'master' into bfdev-configurable-spi-phase-1
2017-06-24 15:27:57 +09:00
jflyper
0c803f23d2
Cherry-picked #3321 (Preset CS lines for SPI devices initial high)
2017-06-24 12:44:01 +09:00
jflyper
7a52f91975
Make SPI pins configurable
2017-06-23 11:12:10 +09:00
jflyper
682d4d4014
Preset CS lines for SPI devices initial high
2017-06-20 21:10:31 +09:00
Sami Korhonen
6ceb35122f
F7 Fix spi init
2017-04-22 08:51:50 +03:00
Martin Budden
2493c214b0
Created subdirectories in drivers directory
2017-04-12 08:06:22 +01:00
Michael Jakob
46387c9dbe
Cleanup ENUM usage
2016-12-04 16:09:21 +01:00
Sami Korhonen
b3a48c1a01
F7 spi rework
2016-11-13 10:07:06 +02:00
Sami Korhonen
a399c14bf9
F7 first try on DMA SDCARD
2016-10-21 08:51:03 +03:00
Sami Korhonen
1f8805cdf0
squash betaflightF7
...
Parts and driver boost from @npsm
2016-10-21 08:51:02 +03:00
Martin Budden
b123e74a73
Receiver code tidy.
2016-10-02 08:45:42 +01:00
Martin Budden
551bbe1d1a
Initial commit of SPI receiver code.
2016-10-02 08:45:42 +01:00
Martin Budden
07adf66bbb
Optimisation of driver header files
2016-08-07 01:14:11 +02:00
JOhn Aughey
c8d25ac7cf
Removing the error condition if the processor isn't known.
2016-07-15 09:37:49 -05:00
Anders Hoglund
2d96e29e07
SPI CS must be driven high also on F1. Some do not have external pullups.
2016-07-08 18:12:47 +02:00
blckmn
688a4ad376
Setup SPI pins for F1 fix
2016-07-06 07:46:38 +10:00
Martin Budden
97fe5afd6c
Converted tabs to spaces.
2016-06-27 19:26:02 +01:00
blckmn
339bd0b0d3
Minor cleanup and rename of fastpwm lookup table
2016-06-24 20:19:03 +10:00
blckmn
95c844b178
Updated CLOCK params to enum following review
2016-06-24 19:43:34 +10:00
blckmn
134bb6f466
Move standard clock to 10.5mhz
2016-06-24 17:28:59 +10:00
blckmn
b8263ec049
SPI1 is on APB2
2016-06-24 09:54:45 +10:00
blckmn
737510062d
Updated 6500 to run at 5.25mhz (rated to 8mhz)
2016-06-24 09:26:03 +10:00
blckmn
9c1c4fef33
SPI to new IO (including SDCARD)
2016-06-03 22:56:45 +10:00
Nicholas Sherlock
84d3cc6175
Basic SDCard block read / write (minimal timeout/error handling)
2016-02-02 23:36:32 +01:00
Nicholas Sherlock
3941c6c252
Delete dubious SPI timeout mechanism
...
The result from this mechanism is never checked, and SPI is not a bus
prone to timeouts anyway (the master generates the clock and the
transmission happens in a deterministic amount of time no matter if the
slave is cooperative, absent, or uncooperative.)
The timeout counter was set *per transfer*, and is fixed no matter what
the SPI clock speed. If the transfer size is large, and the SPI clock is
slow, stalls on the SPI bus are unavoidable (as we can generate data
faster than SPI can transmit it). These accumulate over the length of a
long transfer and trigger a "timeout". Detecting these as fatal timeouts
is not helpful.
2016-02-02 23:36:31 +01:00
Nicholas Sherlock
264c094eef
Add ability to check for SPI bus busy condition
2016-02-02 23:36:31 +01:00
Dominic Clifton
5d49451916
Cleanup SPI on STM32F3 targets.
2015-02-22 21:49:45 +00:00
Nicholas Sherlock
3eb28f16ea
Basic read/write/erase flash functionality works from the CLI
...
Very little code coverage tested yet, only writes of small sizes
2015-01-28 17:45:36 +13:00
Dominic Clifton
d60183d91d
Normalize all the line endings
2014-09-15 23:40:17 +01:00
