mirror of
https://github.com/betaflight/betaflight.git
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190 lines
6 KiB
C
190 lines
6 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "exti.h"
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// MPU6050
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#define MPU_RA_WHO_AM_I 0x75
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#define MPU_RA_WHO_AM_I_LEGACY 0x00
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// RA = Register Address
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#define MPU_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
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#define MPU_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
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#define MPU_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
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#define MPU_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
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#define MPU_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
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#define MPU_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
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#define MPU_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
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#define MPU_RA_XA_OFFS_L_TC 0x07
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#define MPU_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
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#define MPU_RA_YA_OFFS_L_TC 0x09
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#define MPU_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
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#define MPU_RA_ZA_OFFS_L_TC 0x0B
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#define MPU_RA_PRODUCT_ID 0x0C // Product ID Register
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#define MPU_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
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#define MPU_RA_XG_OFFS_USRL 0x14
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#define MPU_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
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#define MPU_RA_YG_OFFS_USRL 0x16
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#define MPU_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
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#define MPU_RA_ZG_OFFS_USRL 0x18
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#define MPU_RA_SMPLRT_DIV 0x19
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#define MPU_RA_CONFIG 0x1A
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#define MPU_RA_GYRO_CONFIG 0x1B
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#define MPU_RA_ACCEL_CONFIG 0x1C
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#define MPU_RA_FF_THR 0x1D
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#define MPU_RA_FF_DUR 0x1E
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#define MPU_RA_MOT_THR 0x1F
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#define MPU_RA_MOT_DUR 0x20
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#define MPU_RA_ZRMOT_THR 0x21
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#define MPU_RA_ZRMOT_DUR 0x22
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#define MPU_RA_FIFO_EN 0x23
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#define MPU_RA_I2C_MST_CTRL 0x24
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#define MPU_RA_I2C_SLV0_ADDR 0x25
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#define MPU_RA_I2C_SLV0_REG 0x26
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#define MPU_RA_I2C_SLV0_CTRL 0x27
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#define MPU_RA_I2C_SLV1_ADDR 0x28
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#define MPU_RA_I2C_SLV1_REG 0x29
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#define MPU_RA_I2C_SLV1_CTRL 0x2A
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#define MPU_RA_I2C_SLV2_ADDR 0x2B
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#define MPU_RA_I2C_SLV2_REG 0x2C
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#define MPU_RA_I2C_SLV2_CTRL 0x2D
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#define MPU_RA_I2C_SLV3_ADDR 0x2E
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#define MPU_RA_I2C_SLV3_REG 0x2F
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#define MPU_RA_I2C_SLV3_CTRL 0x30
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#define MPU_RA_I2C_SLV4_ADDR 0x31
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#define MPU_RA_I2C_SLV4_REG 0x32
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#define MPU_RA_I2C_SLV4_DO 0x33
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#define MPU_RA_I2C_SLV4_CTRL 0x34
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#define MPU_RA_I2C_SLV4_DI 0x35
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#define MPU_RA_I2C_MST_STATUS 0x36
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#define MPU_RA_INT_PIN_CFG 0x37
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#define MPU_RA_INT_ENABLE 0x38
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#define MPU_RA_DMP_INT_STATUS 0x39
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#define MPU_RA_INT_STATUS 0x3A
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#define MPU_RA_ACCEL_XOUT_H 0x3B
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#define MPU_RA_ACCEL_XOUT_L 0x3C
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#define MPU_RA_ACCEL_YOUT_H 0x3D
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#define MPU_RA_ACCEL_YOUT_L 0x3E
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#define MPU_RA_ACCEL_ZOUT_H 0x3F
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#define MPU_RA_ACCEL_ZOUT_L 0x40
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#define MPU_RA_TEMP_OUT_H 0x41
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#define MPU_RA_TEMP_OUT_L 0x42
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#define MPU_RA_GYRO_XOUT_H 0x43
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#define MPU_RA_GYRO_XOUT_L 0x44
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#define MPU_RA_GYRO_YOUT_H 0x45
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#define MPU_RA_GYRO_YOUT_L 0x46
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#define MPU_RA_GYRO_ZOUT_H 0x47
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#define MPU_RA_GYRO_ZOUT_L 0x48
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#define MPU_RA_EXT_SENS_DATA_00 0x49
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#define MPU_RA_MOT_DETECT_STATUS 0x61
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#define MPU_RA_I2C_SLV0_DO 0x63
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#define MPU_RA_I2C_SLV1_DO 0x64
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#define MPU_RA_I2C_SLV2_DO 0x65
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#define MPU_RA_I2C_SLV3_DO 0x66
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#define MPU_RA_I2C_MST_DELAY_CTRL 0x67
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#define MPU_RA_SIGNAL_PATH_RESET 0x68
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#define MPU_RA_MOT_DETECT_CTRL 0x69
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#define MPU_RA_USER_CTRL 0x6A
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#define MPU_RA_PWR_MGMT_1 0x6B
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#define MPU_RA_PWR_MGMT_2 0x6C
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#define MPU_RA_BANK_SEL 0x6D
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#define MPU_RA_MEM_START_ADDR 0x6E
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#define MPU_RA_MEM_R_W 0x6F
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#define MPU_RA_DMP_CFG_1 0x70
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#define MPU_RA_DMP_CFG_2 0x71
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#define MPU_RA_FIFO_COUNTH 0x72
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#define MPU_RA_FIFO_COUNTL 0x73
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#define MPU_RA_FIFO_R_W 0x74
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#define MPU_RA_WHO_AM_I 0x75
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// RF = Register Flag
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#define MPU_RF_DATA_RDY_EN (1 << 0)
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typedef bool (*mpuReadRegisterFunc)(uint8_t reg, uint8_t length, uint8_t* data);
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typedef bool (*mpuWriteRegisterFunc)(uint8_t reg, uint8_t data);
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typedef void(*mpuResetFuncPtr)(void);
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extern mpuResetFuncPtr mpuReset;
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typedef struct mpuConfiguration_s {
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mpuReadRegisterFunc read;
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mpuWriteRegisterFunc write;
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mpuReadRegisterFunc slowread;
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mpuWriteRegisterFunc verifywrite;
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mpuResetFuncPtr reset;
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uint8_t gyroReadXRegister; // Y and Z must registers follow this, 2 words each
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} mpuConfiguration_t;
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enum gyro_fsr_e {
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INV_FSR_250DPS = 0,
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INV_FSR_500DPS,
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INV_FSR_1000DPS,
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INV_FSR_2000DPS,
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NUM_GYRO_FSR
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};
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enum fchoice_b {
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FCB_DISABLED = 0,
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FCB_8800_32,
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FCB_3600_32
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};
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enum clock_sel_e {
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INV_CLK_INTERNAL = 0,
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INV_CLK_PLL,
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NUM_CLK
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};
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enum accel_fsr_e {
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INV_FSR_2G = 0,
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INV_FSR_4G,
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INV_FSR_8G,
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INV_FSR_16G,
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NUM_ACCEL_FSR
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};
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typedef enum {
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MPU_NONE,
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MPU_3050,
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MPU_60x0,
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MPU_60x0_SPI,
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MPU_65xx_I2C,
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MPU_65xx_SPI,
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MPU_9250_SPI,
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ICM_20689_SPI
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} detectedMPUSensor_e;
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typedef enum {
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MPU_HALF_RESOLUTION,
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MPU_FULL_RESOLUTION
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} mpu6050Resolution_e;
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typedef struct mpuDetectionResult_s {
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detectedMPUSensor_e sensor;
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mpu6050Resolution_e resolution;
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} mpuDetectionResult_t;
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struct gyroDev_s;
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void mpuGyroInit(struct gyroDev_s *gyro);
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struct accDev_s;
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bool mpuAccRead(struct accDev_s *acc);
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bool mpuGyroRead(struct gyroDev_s *gyro);
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mpuDetectionResult_t *mpuDetect(struct gyroDev_s *gyro);
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bool mpuCheckDataReady(struct gyroDev_s *gyro);
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