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The H730 is a value-line CPU, similar to the H723/H725, but with only 128kb RAM. The FC firmware code is designed to RUN from external flash in MEMORY MAPPED mode, via OctoSPI. Use of ITCM/DTCM advised for core loops, like PID control. A bootloader is required to enable memory-mapped mode and jump to the firmware, similar to how EXST bootloader system works. Config storage is not part of this commit and is a problem when using a single flash chip in memory mapped mode because the CPU can't run read/write routines from the flash chip while writing to the flash chip. Until flash read/write routines are updated the solution requires either a second flash chip on an SPI interface, or the use of an SD card for config storage. Additional commits will support read/write of config to the code/data storage flash chip to enable cheap and space efficient single-flash-chip FC solutions. Squashed commits: STM32H730 - Workaround issue with 2GB `.elf` files being created. STM32H730 - Reduce firmware size to 1MB. STM32H730 - Add USB HS configuration. STM32H730 - Add ADC internal tag mappings. STM32H730 - Update all ADC mappings based on the referenced ST documentation. Add the VBAT channels. STM32H730 - Fix DMA continuous requests. STM32H730 - Fix ADC_INTERNAL confusion. STM32H730/G4 - Disambiguate use of ADC_CHANNEL_INTERNAL_FIRST_ID. STM32H730 - Fix documentation reference. STM32H730 - Add DMA request mapping for ADC3. STM32H730 - Explicitly set the ADC clock. STM32H730 - Configure PLL2 speeds correctly. * Tested with Ultrafast 64GB SanDisk SDXC card. STM32H730 - Use 50Mhz clock for SDXC cards. * Tested with SanDisk Ultra 64GB. 100Mhz clock gave CRC errors. STM32H730 - Ensure USB has a lower NVIC priority than the SDMMC card reads. If it's higher, 0, then the SDMMC's DMA IRQ handler doesn't get called when handing USB MSC storage reads. STM32H730 - Support CPU name in CLI. STM32H730 - Rebuild when linker scripts changes.
174 lines
4.6 KiB
Text
174 lines
4.6 KiB
Text
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(STACKRAM) + LENGTH(STACKRAM); /* end of RAM */
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/* Base address where the quad spi. */
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__octospi1_start = ORIGIN(OCTOSPI1);
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__octospi2_start = ORIGIN(OCTOSPI2);
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0; /* required amount of heap */
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_Min_Stack_Size = 0x800; /* required amount of stack */
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/* Define output sections */
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SECTIONS
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{
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_isr_vector_table_flash_base = LOADADDR(.isr_vector);
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PROVIDE (isr_vector_table_flash_base = _isr_vector_table_flash_base);
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.isr_vector :
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{
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. = ALIGN(512);
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PROVIDE (isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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PROVIDE (isr_vector_table_end = .);
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} >VECTAB AT> MAIN
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_ram_isr_vector_table_base = LOADADDR(.ram_isr_vector);
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PROVIDE (ram_isr_vector_table_base = _ram_isr_vector_table_base);
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.ram_isr_vector (NOLOAD) :
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{
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. = ALIGN(512); /* Vector table offset must be multiple of 0x200 */
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PROVIDE (ram_isr_vector_table_base = .);
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. += (isr_vector_table_end - isr_vector_table_base);
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. = ALIGN(4);
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PROVIDE (ram_isr_vector_table_end = .);
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} >DTCM_RAM
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/* The program code and other data goes into MAIN */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >MAIN
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/* Critical program code goes into ITCM RAM */
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/* Copy specific fast-executing code to ITCM RAM */
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tcm_code = LOADADDR(.tcm_code);
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.tcm_code :
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{
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. = ALIGN(4);
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tcm_code_start = .;
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*(.tcm_code)
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*(.tcm_code*)
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. = ALIGN(4);
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tcm_code_end = .;
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} >ITCM_RAM AT >MAIN
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >MAIN
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.ARM :
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{
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__exidx_start = .;
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*(.ARM.exidx*) __exidx_end = .;
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} >MAIN
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.pg_registry :
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{
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PROVIDE_HIDDEN (__pg_registry_start = .);
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KEEP (*(.pg_registry))
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KEEP (*(SORT(.pg_registry.*)))
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PROVIDE_HIDDEN (__pg_registry_end = .);
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} >MAIN
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.pg_resetdata :
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{
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PROVIDE_HIDDEN (__pg_resetdata_start = .);
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KEEP (*(.pg_resetdata))
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PROVIDE_HIDDEN (__pg_resetdata_end = .);
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} >MAIN
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >DTCM_RAM AT >MAIN
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* Uninitialized data section */
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. = ALIGN(4);
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.sram2 (NOLOAD) :
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{
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/* This is used by the startup in order to initialize the .sram2 secion */
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_ssram2 = .; /* define a global symbol at sram2 start */
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__sram2_start__ = _ssram2;
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*(.sram2)
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*(SORT_BY_ALIGNMENT(.sram2*))
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. = ALIGN(4);
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_esram2 = .; /* define a global symbol at sram2 end */
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__sram2_end__ = _esram2;
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} >RAM
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/* used during startup to initialized fastram_data */
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_sfastram_idata = LOADADDR(.fastram_data);
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/* Initialized FAST_DATA section for unsuspecting developers */
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.fastram_data :
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{
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. = ALIGN(4);
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_sfastram_data = .; /* create a global symbol at data start */
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*(.fastram_data) /* .data sections */
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*(.fastram_data*) /* .data* sections */
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. = ALIGN(4);
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_efastram_data = .; /* define a global symbol at data end */
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} >FASTRAM AT >MAIN
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. = ALIGN(4);
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.fastram_bss (NOLOAD) :
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{
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_sfastram_bss = .;
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__fastram_bss_start__ = _sfastram_bss;
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*(.fastram_bss)
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*(SORT_BY_ALIGNMENT(.fastram_bss*))
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. = ALIGN(4);
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_efastram_bss = .;
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__fastram_bss_end__ = _efastram_bss;
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} >FASTRAM
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}
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