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87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*
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modified version of StdPeriph function is located here.
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TODO - what license does apply here?
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original file was lincesed under MCD-ST Liberty SW License Agreement V2
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http://www.st.com/software_license_agreement_liberty_v2
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*/
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#include "stm32f4xx.h"
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#include "timer.h"
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#include "rcc.h"
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/**
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* @brief Selects the TIM Output Compare Mode.
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* @note This function does NOT disable the selected channel before changing the Output
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* Compare Mode.
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* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
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* @param TIM_Channel: specifies the TIM Channel
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* This parameter can be one of the following values:
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* @arg TIM_Channel_1: TIM Channel 1
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* @arg TIM_Channel_2: TIM Channel 2
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* @arg TIM_Channel_3: TIM Channel 3
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* @arg TIM_Channel_4: TIM Channel 4
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* @param TIM_OCMode: specifies the TIM Output Compare Mode.
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* This parameter can be one of the following values:
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* @arg TIM_OCMode_Timing
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* @arg TIM_OCMode_Active
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* @arg TIM_OCMode_Toggle
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* @arg TIM_OCMode_PWM1
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* @arg TIM_OCMode_PWM2
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* @arg TIM_ForcedAction_Active
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* @arg TIM_ForcedAction_InActive
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* @retval None
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*/
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#define CCMR_Offset ((uint16_t)0x0018)
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const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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{ .TIMx = TIM1, .rcc = RCC_APB2(TIM1) },
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{ .TIMx = TIM2, .rcc = RCC_APB1(TIM2) },
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{ .TIMx = TIM3, .rcc = RCC_APB1(TIM3) },
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{ .TIMx = TIM4, .rcc = RCC_APB1(TIM4) },
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{ .TIMx = TIM5, .rcc = RCC_APB1(TIM5) },
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{ .TIMx = TIM6, .rcc = RCC_APB1(TIM6) },
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{ .TIMx = TIM7, .rcc = RCC_APB1(TIM7) },
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{ .TIMx = TIM8, .rcc = RCC_APB2(TIM8) },
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{ .TIMx = TIM9, .rcc = RCC_APB2(TIM9) },
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{ .TIMx = TIM10, .rcc = RCC_APB2(TIM10) },
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{ .TIMx = TIM11, .rcc = RCC_APB2(TIM11) },
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{ .TIMx = TIM12, .rcc = RCC_APB1(TIM12) },
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{ .TIMx = TIM13, .rcc = RCC_APB1(TIM13) },
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{ .TIMx = TIM14, .rcc = RCC_APB1(TIM14) },
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};
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void TIM_SelectOCxM_NoDisable(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
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{
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uint32_t tmp = 0;
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/* Check the parameters */
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assert_param(IS_TIM_LIST8_PERIPH(TIMx));
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assert_param(IS_TIM_CHANNEL(TIM_Channel));
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assert_param(IS_TIM_OCM(TIM_OCMode));
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tmp = (uint32_t) TIMx;
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tmp += CCMR_Offset;
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if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
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{
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tmp += (TIM_Channel>>1);
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/* Reset the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
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/* Configure the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp |= TIM_OCMode;
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}
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else
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{
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tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
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/* Reset the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
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/* Configure the OCxM bits in the CCMRx register */
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*(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
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}
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}
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