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@ -1,559 +0,0 @@
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/**
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******************************************************************************
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* @file system_stm32f2xx.c
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* @author MCD Application Team
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* @version V1.1.3
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* @date 05-March-2012
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F2xx devices,
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* and is generated by the clock configuration tool
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* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f2xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (16 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and HSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
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* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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*=============================================================================
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* Supported STM32F2xx device revision | Rev B and Y
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 120000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 120000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 4
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 25000000
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*-----------------------------------------------------------------------------
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* PLL_M | 25
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*-----------------------------------------------------------------------------
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* PLL_N | 240
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*-----------------------------------------------------------------------------
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* PLL_P | 2
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*-----------------------------------------------------------------------------
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* PLL_Q | 5
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 3
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Enabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f2xx_system
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* @{
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*/
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/** @addtogroup STM32F2xx_System_Private_Includes
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* @{
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*/
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#include "stm32f2xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to use external SRAM mounted
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on STM322xG_EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
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// Gives 60MHz
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#define PLL_M 12
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#define PLL_N 240
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 5
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 60000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
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* @{
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*/
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extern uint32_t Master_frequency ;
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uint32_t Peri1_frequency ;
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uint32_t Peri2_frequency ;
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uint32_t Timer_mult1 ;
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uint32_t Timer_mult2 ;
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static void SetSysClock(void);
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings ----------------------------------*/
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SetSysClock();
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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extern uint32_t g_pfnVectors ;
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SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
|
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
|
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
|
||||
case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
|
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
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if (pllsource != 0)
|
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{
|
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/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
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{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
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}
|
||||
|
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
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/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
Master_frequency = 60000000 ;
|
||||
Peri1_frequency = 15000000 ;
|
||||
Peri2_frequency = 30000000 ;
|
||||
Timer_mult1 = 2 ;
|
||||
Timer_mult2 = 2 ;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f2xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM322xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
|
||||
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
|
||||
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
|
||||
+-------------------+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR = 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcc0ccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xa2aa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xf3ff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xc00000cc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaa800a;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffc00f;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010400;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 0;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 4;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -1,819 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_storage_msd.c
|
||||
* @author MCD application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the disk operations functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "../src/targets/taranis/i2c.h"
|
||||
#include "../src/keys.h"
|
||||
#include "../src/eeprom_rlc.h"
|
||||
extern "C" {
|
||||
#include "../src/FatFs/diskio.h"
|
||||
}
|
||||
//#include "board_taranis.h"
|
||||
|
||||
#include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h"
|
||||
#include "hal.h"
|
||||
#define SD_CARD_PRESENT() (~SD_PRESENT_GPIO->IDR & SD_PRESENT_GPIO_Pin)
|
||||
|
||||
void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) ;
|
||||
void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size);
|
||||
|
||||
extern "C" {
|
||||
#include "misc.h"
|
||||
#include "usbd_msc_mem.h"
|
||||
#include "usb_conf.h"
|
||||
|
||||
#define eeWriteBlockCmp I2C_EE_BufferWrite
|
||||
#define eeprom_read_block I2C_EE_BufferRead
|
||||
|
||||
|
||||
#define STORAGE_LUN_NBR 2
|
||||
#define BLOCKSIZE 512
|
||||
|
||||
/* USB Mass storage Standard Inquiry Data */
|
||||
const unsigned char STORAGE_Inquirydata[] = {//36
|
||||
|
||||
/* LUN 0 */
|
||||
0x00,
|
||||
0x80,
|
||||
0x02,
|
||||
0x02,
|
||||
(USBD_STD_INQUIRY_LENGTH - 5),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
|
||||
'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */
|
||||
'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ',
|
||||
'1', '.', '0', '0', /* Version : 4 Bytes */
|
||||
/* LUN 1 */
|
||||
0x00,
|
||||
0x80,
|
||||
0x02,
|
||||
0x02,
|
||||
(USBD_STD_INQUIRY_LENGTH - 5),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
|
||||
'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */
|
||||
'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ',
|
||||
'1', '.', '0' ,'0', /* Version : 4 Bytes */
|
||||
};
|
||||
|
||||
int32_t fat12Write( const uint8_t *buffer, uint16_t sector, uint32_t count ) ;
|
||||
int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count ) ;
|
||||
|
||||
int8_t STORAGE_Init (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_GetCapacity (uint8_t lun,
|
||||
uint32_t *block_num,
|
||||
uint32_t *block_size);
|
||||
|
||||
int8_t STORAGE_IsReady (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_IsWriteProtected (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_Read (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len);
|
||||
|
||||
int8_t STORAGE_Write (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len);
|
||||
|
||||
int8_t STORAGE_GetMaxLun (void);
|
||||
|
||||
USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops =
|
||||
{
|
||||
STORAGE_Init,
|
||||
STORAGE_GetCapacity,
|
||||
STORAGE_IsReady,
|
||||
STORAGE_IsWriteProtected,
|
||||
STORAGE_Read,
|
||||
STORAGE_Write,
|
||||
STORAGE_GetMaxLun,
|
||||
(int8_t *)STORAGE_Inquirydata,
|
||||
};
|
||||
|
||||
USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops;
|
||||
|
||||
__IO uint32_t count = 0;
|
||||
}
|
||||
|
||||
int8_t STORAGE_Init (uint8_t lun)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
/* TODO if no SD ... if( SD_Init() != 0)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
*/
|
||||
return (0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return medium capacity and block size
|
||||
* @param lun : logical unit number
|
||||
* @param block_num : number of physical block
|
||||
* @param block_size : size of a physical block
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size)
|
||||
{
|
||||
if (lun == 1) {
|
||||
*block_size = BLOCKSIZE;
|
||||
*block_num = EESIZE/BLOCKSIZE + 3 + 1024 ;
|
||||
}
|
||||
else {
|
||||
if (!SD_CARD_PRESENT())
|
||||
return -1;
|
||||
|
||||
*block_size = BLOCKSIZE;
|
||||
|
||||
static DWORD sector_count = 0;
|
||||
if (sector_count == 0) {
|
||||
if (disk_ioctl(0, GET_SECTOR_COUNT, §or_count) != RES_OK) {
|
||||
sector_count = 0;
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
*block_num = sector_count;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the medium is ready
|
||||
* @param lun : logical unit number
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_IsReady (uint8_t lun)
|
||||
{
|
||||
if (lun == 1) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
return SD_CARD_PRESENT() ? 0 : -1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the medium is write-protected
|
||||
* @param lun : logical unit number
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_IsWriteProtected (uint8_t lun)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read data from the medium
|
||||
* @param lun : logical unit number
|
||||
* @param buf : Pointer to the buffer to save data
|
||||
* @param blk_addr : address of 1st block to be read
|
||||
* @param blk_len : nmber of blocks to be read
|
||||
* @retval Status
|
||||
*/
|
||||
|
||||
int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count);
|
||||
|
||||
int8_t STORAGE_Read (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len)
|
||||
{
|
||||
if (lun == 1) {
|
||||
if (fat12Read(buf, blk_addr, blk_len) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (SD_ReadSectors(buf,
|
||||
blk_addr,
|
||||
blk_len) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Write data to the medium
|
||||
* @param lun : logical unit number
|
||||
* @param buf : Pointer to the buffer to write from
|
||||
* @param blk_addr : address of 1st block to be written
|
||||
* @param blk_len : nmber of blocks to be read
|
||||
* @retval Status
|
||||
*/
|
||||
|
||||
int8_t SD_WriteSectors(uint8_t *buf, uint32_t sector, uint32_t count);
|
||||
|
||||
int8_t STORAGE_Write (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len)
|
||||
{
|
||||
if (lun == 1) {
|
||||
if (fat12Write(buf, blk_addr, blk_len) != 0)
|
||||
return -1;
|
||||
}
|
||||
else {
|
||||
if (SD_WriteSectors(buf,
|
||||
blk_addr,
|
||||
blk_len) != 0)
|
||||
return -1;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return number of supported logical unit
|
||||
* @param None
|
||||
* @retval number of logical unit
|
||||
*/
|
||||
|
||||
int8_t STORAGE_GetMaxLun (void)
|
||||
{
|
||||
return (STORAGE_LUN_NBR - 1);
|
||||
}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/**
|
||||
* FAT12 boot sector partition.
|
||||
*/
|
||||
const char g_FATboot[BLOCKSIZE] =
|
||||
{
|
||||
0xeb, 0x3c, 0x90, // Jump instruction.
|
||||
0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name
|
||||
0x00, 0x02, // Bytes per sector
|
||||
0x08, // Sectors per FS cluster.
|
||||
0x01, 0x00, // Reserved sector count
|
||||
|
||||
0x01, // Number of FATs
|
||||
0x10, 0x00, // Number of root directory entries
|
||||
(EESIZE/BLOCKSIZE)+3, 0x04, // Total sectors = 1024+131=1155
|
||||
0xf8, // Media descriptor
|
||||
0x01, 0x00, // Sectors per FAT table
|
||||
0x20, 0x00, // Sectors per track
|
||||
0x40, 0x00, // Number of heads
|
||||
0x00, 0x00, 0x00, 0x00, // Number of hidden sectors
|
||||
|
||||
0x00, 0x00, 0x00, 0x00, // Large number of sectors.
|
||||
0x00, // Physical drive number
|
||||
0x00, // Reserved
|
||||
0x29, // Extended boot signature
|
||||
0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number)
|
||||
0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label
|
||||
0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type
|
||||
0x00, 0x00, // OS boot code
|
||||
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa
|
||||
};
|
||||
|
||||
#if defined(REV4a)
|
||||
const char g_FAT[BLOCKSIZE] =
|
||||
{
|
||||
0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B,
|
||||
0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60,
|
||||
0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02,
|
||||
0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B,
|
||||
0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60,
|
||||
0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04,
|
||||
0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B,
|
||||
0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60,
|
||||
0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06,
|
||||
0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B,
|
||||
0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60,
|
||||
0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08,
|
||||
0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
#else
|
||||
const char g_FAT[BLOCKSIZE] =
|
||||
{
|
||||
0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B,
|
||||
0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60,
|
||||
0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02,
|
||||
0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B,
|
||||
0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60,
|
||||
0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04,
|
||||
0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B,
|
||||
0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60,
|
||||
0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06,
|
||||
0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B,
|
||||
0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60,
|
||||
0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08,
|
||||
0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
#endif
|
||||
|
||||
// File Attributes
|
||||
// 0 0x01 Read Only.
|
||||
// 1 0x02 Hidden.
|
||||
// 2 0x04 System.
|
||||
// 3 0x08 Volume Label.
|
||||
// 4 0x10 Subdirectory.
|
||||
// 5 0x20 Archive.
|
||||
// 6 0x40 Device.
|
||||
// 7 0x80 Reserved.
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t name[8];
|
||||
uint8_t ext[3];
|
||||
uint8_t attribute;
|
||||
uint8_t reserved;
|
||||
uint8_t create_time_ms;
|
||||
uint16_t create_time;
|
||||
uint16_t create_date;
|
||||
uint16_t access_date;
|
||||
uint16_t ea_index;
|
||||
uint16_t modify_time;
|
||||
uint16_t modify_date;
|
||||
uint16_t start_cluster;
|
||||
uint32_t file_size;
|
||||
} FATDirEntry_t;
|
||||
|
||||
// First 16 FAT root directory entries (1 sector)
|
||||
const FATDirEntry_t g_DIRroot[16] =
|
||||
{
|
||||
{
|
||||
#ifdef PCBTARANIS
|
||||
{ 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
#else
|
||||
{ 'E', 'R', 'S', 'K', 'Y', '_', '9', 'X'},
|
||||
{ ' ', ' ', ' '},
|
||||
#endif
|
||||
0x08, // Volume
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
#ifdef PCBTARANIS
|
||||
{ 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '},
|
||||
{ 'B', 'I', 'N'},
|
||||
#else
|
||||
{ 'E', 'R', 'S', 'K', 'Y', '9', 'X', ' '},
|
||||
{ 'B', 'I', 'N'},
|
||||
#endif
|
||||
0x24, // Archive, hidden, system
|
||||
0x00,
|
||||
0x3E,
|
||||
0xA301,
|
||||
0x3D55,
|
||||
0x3D55,
|
||||
0x0000,
|
||||
0xA302,
|
||||
0x3D55,
|
||||
0x0002,
|
||||
EESIZE
|
||||
},
|
||||
{
|
||||
{ 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'},
|
||||
{ 'B', 'I', 'N'},
|
||||
0x24, // Archive, hidden, system
|
||||
0x00,
|
||||
0x3E,
|
||||
0xA301,
|
||||
0x3D55,
|
||||
0x3D55,
|
||||
0x0000,
|
||||
0xA302,
|
||||
0x3D55,
|
||||
0x000A,
|
||||
0x00080000 // 512K
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
{
|
||||
{ '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '},
|
||||
{ ' ', ' ', ' '},
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x00000000
|
||||
},
|
||||
};
|
||||
|
||||
// count is number of 512 byte sectors
|
||||
int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count )
|
||||
{
|
||||
while ( count )
|
||||
{
|
||||
if (sector == 0) {
|
||||
memcpy( buffer, g_FATboot, BLOCKSIZE ) ;
|
||||
}
|
||||
else if (sector == 1/*Reserved sector count*/) {
|
||||
// FAT table.
|
||||
memcpy( buffer, g_FAT, BLOCKSIZE);
|
||||
}
|
||||
else if (sector == 2) {
|
||||
memcpy( buffer, g_DIRroot, BLOCKSIZE ) ;
|
||||
}
|
||||
else if ( sector < 67 )
|
||||
{
|
||||
eeprom_read_block (buffer, (sector-3)*BLOCKSIZE, BLOCKSIZE);
|
||||
}
|
||||
else if ( sector < 1155 )
|
||||
{
|
||||
uint32_t address ;
|
||||
address = sector - 67 ;
|
||||
address *= 512 ;
|
||||
address += 0x08000000 ;
|
||||
memcpy( buffer, (uint8_t *)address, BLOCKSIZE ) ;
|
||||
}
|
||||
buffer += BLOCKSIZE ;
|
||||
sector++ ;
|
||||
count-- ;
|
||||
}
|
||||
return 0 ;
|
||||
}
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
extern uint32_t program( uint32_t *address, uint32_t *buffer ) ; // size is 256 bytes
|
||||
|
||||
uint32_t isValidEepromStart( const uint8_t *buffer )
|
||||
{
|
||||
uint32_t size ;
|
||||
uint32_t bs ;
|
||||
// Check Taranis format
|
||||
size = buffer[1] + ( buffer[2] << 8 ) ;
|
||||
bs = buffer[5] ;
|
||||
if ( ( size == 0x0100 ) && ( bs == 0x40 ) )
|
||||
{
|
||||
return 1 ;
|
||||
}
|
||||
size = buffer[1] ;
|
||||
bs = buffer[3] ;
|
||||
if ( ( size == 0x0080 ) && ( bs == 0x80 ) )
|
||||
{
|
||||
return 1 ;
|
||||
}
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
int32_t fat12Write(const uint8_t *buffer, uint16_t sector, uint32_t count )
|
||||
{
|
||||
static int offset = 0;
|
||||
|
||||
// TRACE("FAT12 Write(sector=%d, count=%d)", sector, count);
|
||||
|
||||
if ( sector >= 3 )
|
||||
{
|
||||
if ( sector < 67 )
|
||||
{
|
||||
while (count)
|
||||
{
|
||||
if (offset == 0 && sector == 3 &&/*test->version==EEFS_VERS && */ isValidEepromStart( buffer ) )
|
||||
{
|
||||
// TRACE("EEPROM start found in sector %d", sector);
|
||||
offset = sector;
|
||||
}
|
||||
if (offset && sector >= offset && (sector-offset) < EESIZE/BLOCKSIZE)
|
||||
{
|
||||
eeWriteBlockCmp((uint8_t *)buffer, (sector-offset)*BLOCKSIZE, BLOCKSIZE);
|
||||
}
|
||||
buffer += BLOCKSIZE;
|
||||
sector++;
|
||||
count--;
|
||||
if (sector-offset >= EESIZE/BLOCKSIZE)
|
||||
{
|
||||
// TRACE("EEPROM end written at sector %d", sector-1);
|
||||
offset = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ( sector < 1155 )
|
||||
{
|
||||
// firmware
|
||||
uint32_t address ;
|
||||
address = sector - 67 ;
|
||||
address *= 512 ;
|
||||
address += 0x08000000 ;
|
||||
|
||||
uint32_t i ;
|
||||
while ( count )
|
||||
{
|
||||
for ( i = 0 ; i < 2 ; i += 1 )
|
||||
{
|
||||
if ( address >= 0x08008000 ) // Protect bootloader
|
||||
{
|
||||
if ( address < (0x08000000 + (512*1024) - 256) ) // in range
|
||||
{
|
||||
program( (uint32_t *)address, (uint32_t *) buffer ) ; // size is 256 bytes
|
||||
}
|
||||
}
|
||||
address += 256 ;
|
||||
buffer += 256 ;
|
||||
}
|
||||
count -= 1 ;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -638,10 +638,11 @@ ifeq ($(PCB), TARANIS)
|
|||
BOARDSRC = targets/taranis/board_taranis.cpp
|
||||
EXTRABOARDSRC += targets/taranis/lcd_driver.cpp targets/taranis/aspi.c targets/taranis/i2c.c targets/taranis/delays.c
|
||||
SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c
|
||||
SRC += targets/taranis/pwr_driver.c
|
||||
EEPROMSRC = eeprom_common.cpp eeprom_rlc.cpp eeprom_conversions.cpp
|
||||
PULSESSRC = protocols/pulses_arm.cpp protocols/ppm_arm.cpp protocols/pxx_arm.cpp
|
||||
CPPSRC += audio_arm.cpp
|
||||
CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp
|
||||
CPPSRC += targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp
|
||||
CPPSRC += bmp.cpp gui/view_channels.cpp gui/view_about.cpp gui/view_text.cpp
|
||||
SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
|
||||
SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c
|
||||
|
@ -1097,14 +1098,14 @@ all: begin gccversion sizebefore build sizeafter end
|
|||
ifeq ($(ARCH), AVR)
|
||||
build: stamp_header tra lbm allsrc.cpp elf remallsrc hex
|
||||
else
|
||||
build: stamp_header tra lbm bootloader allsrc.cpp elf remallsrc bin
|
||||
build: stamp_header tra lbm bootloader.lbm allsrc.cpp elf remallsrc bin
|
||||
endif
|
||||
|
||||
# build bootloader
|
||||
.PHONY bootloader:
|
||||
.PHONY bootloader.lbm:
|
||||
@echo "Building bootloader..."
|
||||
$(MAKE) -C ../bootloader PCB=$(PCB)
|
||||
$(BIN2LBM) bootloader.lbm ../bootloader/bootloader_ramBoot.bin
|
||||
$(MAKE) -C bootloader PCB=$(PCB)
|
||||
$(BIN2LBM) bootloader.lbm bootloader/bootloader_ramBoot.bin
|
||||
|
||||
tra: translations/en.h translations/cz.h translations/de.h translations/es.h translations/fi.h translations/fr.h translations/it.h translations/pl.h translations/pt.h translations/se.h
|
||||
lbm: fonts bitmaps/sticks.lbm
|
||||
|
@ -1365,7 +1366,7 @@ clean_list :
|
|||
$(REMOVE) allsrc.cpp
|
||||
$(REMOVE) stamp-opentx.h
|
||||
$(REMOVE) `find . -name "*.lbm"`
|
||||
$(MAKE) -C ../bootloader clean
|
||||
$(MAKE) -C bootloader clean
|
||||
|
||||
#### Install
|
||||
|
||||
|
|
|
@ -93,18 +93,18 @@ ifeq ($(RUN_FROM_FLASH), 1)
|
|||
else
|
||||
ifeq ($(PCB), TARANIS)
|
||||
ARCH = ARM
|
||||
LDSCRIPT = stm32_ramBoot.ld
|
||||
LDSCRIPT = ../targets/taranis/stm32_ramBoot.ld
|
||||
TRGT = arm-none-eabi-
|
||||
CPPDEFS += -DHSE_VALUE=12000000
|
||||
CPPDEFS += -DPCBTARANIS
|
||||
FULL_PRJ = $(PROJECT)_ramBoot
|
||||
EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc
|
||||
EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include
|
||||
EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc
|
||||
EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc
|
||||
EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc
|
||||
EXTRAINCDIRS += ../src/targets/taranis
|
||||
EXTRAINCDIRS += ../src/fonts/std
|
||||
EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc
|
||||
EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include
|
||||
EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc
|
||||
EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc
|
||||
EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc
|
||||
EXTRAINCDIRS += ../targets/taranis
|
||||
EXTRAINCDIRS += ../fonts/std
|
||||
endif
|
||||
endif
|
||||
|
||||
|
@ -115,43 +115,43 @@ endif
|
|||
UADEFS =
|
||||
|
||||
ifeq ($(PCB), TARANIS)
|
||||
SRC = system_stm32f2xx.c \
|
||||
../src/targets/taranis/i2c.c \
|
||||
../src/targets/taranis/delays.c \
|
||||
../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \
|
||||
../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \
|
||||
../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \
|
||||
../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \
|
||||
../src/FatFs/ff.c \
|
||||
../src/FatFs/option/ccsbcs.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \
|
||||
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \
|
||||
../src/targets/taranis/usbd_desc.c \
|
||||
../src/targets/taranis/aspi.c \
|
||||
../src/targets/taranis/usb_bsp.c \
|
||||
../src/targets/taranis/usb_driver.c \
|
||||
../src/targets/taranis/pwr_driver.c
|
||||
SRC = ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c \
|
||||
../targets/taranis/i2c.c \
|
||||
../targets/taranis/delays.c \
|
||||
../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \
|
||||
../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \
|
||||
../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \
|
||||
../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \
|
||||
../FatFs/ff.c \
|
||||
../FatFs/option/ccsbcs.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \
|
||||
../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \
|
||||
../targets/taranis/usbd_desc.c \
|
||||
../targets/taranis/aspi.c \
|
||||
../targets/taranis/usb_bsp.c \
|
||||
../targets/taranis/usb_driver.c \
|
||||
../targets/taranis/pwr_driver.c
|
||||
|
||||
CPPSRC = ../src/targets/taranis/lcd_driver.cpp \
|
||||
../src/targets/taranis/keys_driver.cpp \
|
||||
../src/targets/taranis/diskio.cpp \
|
||||
../src/targets/taranis/usbd_usr.cpp \
|
||||
usbd_storage_msd.cpp \
|
||||
../src/lcd.cpp \
|
||||
../src/keys.cpp \
|
||||
../src/fonts.cpp \
|
||||
CPPSRC = ../targets/taranis/lcd_driver.cpp \
|
||||
../targets/taranis/keys_driver.cpp \
|
||||
../targets/taranis/diskio.cpp \
|
||||
../targets/taranis/usbd_usr.cpp \
|
||||
../targets/taranis/usbd_storage_msd.cpp \
|
||||
../lcd.cpp \
|
||||
../keys.cpp \
|
||||
../fonts.cpp \
|
||||
boot.cpp
|
||||
|
||||
# List ASM source files here
|
||||
ASRC = ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s
|
||||
ASRC = ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s
|
||||
|
||||
else
|
||||
|
|
@ -57,13 +57,13 @@
|
|||
#ifdef PCBTARANIS
|
||||
#include "stm32f2xx.h"
|
||||
#include "stm32f2xx_flash.h"
|
||||
#include "../src/targets/taranis/i2c.h"
|
||||
#include "../targets/taranis/i2c.h"
|
||||
#include "hal.h"
|
||||
|
||||
extern "C" {
|
||||
#include "usb_dcd_int.h"
|
||||
#include "usb_bsp.h"
|
||||
#include "../src/targets/taranis/usbd_desc.h"
|
||||
#include "../targets/taranis/usbd_desc.h"
|
||||
#include "usbd_msc_core.h"
|
||||
#include "usbd_usr.h"
|
||||
}
|
||||
|
@ -71,12 +71,12 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#include "board_taranis.h"
|
||||
#include "../src/pwr.h"
|
||||
#include "../src/lcd.h"
|
||||
#include "../src/keys.h"
|
||||
#include "../pwr.h"
|
||||
#include "../lcd.h"
|
||||
#include "../keys.h"
|
||||
|
||||
#include "../src/FatFs/ff.h"
|
||||
#include "../src/FatFs/diskio.h"
|
||||
#include "../FatFs/ff.h"
|
||||
#include "../FatFs/diskio.h"
|
||||
|
||||
#ifdef PCBTARANIS
|
||||
#define BOOT_KEY_UP KEY_PLUS
|
|
@ -36,7 +36,7 @@
|
|||
|
||||
#include "../../opentx.h"
|
||||
|
||||
bool dacIdle = true;
|
||||
int dacIdle = 1;
|
||||
|
||||
void setSampleRate(uint32_t frequency)
|
||||
{
|
||||
|
@ -96,7 +96,7 @@ void dacInit()
|
|||
bool dacQueue(AudioBuffer *buffer)
|
||||
{
|
||||
if (dacIdle) {
|
||||
dacIdle = false;
|
||||
dacIdle = 0;
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA channel
|
||||
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
|
||||
DMA1_Stream5->M0AR = CONVERT_PTR(buffer->data);
|
||||
|
@ -149,7 +149,7 @@ extern "C" void DMA1_Stream5_IRQHandler()
|
|||
DAC->SR = DAC_SR_DMAUDR1; // Write 1 to clear flag
|
||||
}
|
||||
else {
|
||||
dacIdle = true;
|
||||
dacIdle = 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -42,7 +42,7 @@ extern void audioEnd( void ) ;
|
|||
|
||||
extern void setSampleRate(uint32_t frequency);
|
||||
|
||||
extern bool dacIdle;
|
||||
extern int dacIdle;
|
||||
|
||||
inline void dacStart()
|
||||
{
|
||||
|
|
|
@ -35,7 +35,7 @@
|
|||
*/
|
||||
|
||||
#include "board_taranis.h"
|
||||
#include "../src/pwr.h"
|
||||
#include "../pwr.h"
|
||||
|
||||
void pwrInit()
|
||||
{
|
||||
|
|
|
@ -26,8 +26,8 @@
|
|||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../opentx.h"
|
||||
#include "../FatFs/diskio.h"
|
||||
#include "../../opentx.h"
|
||||
#include "../../FatFs/diskio.h"
|
||||
#include "board_taranis.h"
|
||||
|
||||
extern "C" {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue