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add at32 bsp driver lib

Browse source 
Co-Authored-By: EMSR <10240646+shanggl@users.noreply.github.com>
Co-Authored-By: carl <101383042+tcdddd@users.noreply.github.com>
Co-Authored-By: Hugo Chiang <hugo@gyroflow.xyz>
This commit is contained in:
EMSR 2023-01-29 22:53:45 +08:00 • committed by Hugo Chiang
parent b355551789
commit 389e9e9bc8
139 changed files with 135899 additions and 1 deletions
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1
CMakeLists.txt
View file

@ -71,6 +71,7 @@ set(COMMON_COMPILE_DEFINITIONS
include(openocd)
include(svd)
include(stm32)
include(at32)
add_subdirectory(src)

9
board/at32fc.cfg Normal file
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@ -0,0 +1,9 @@
# Boardconfig for AT-LINK for AT32F4-FC
source [find interface/atlink.cfg]
#transport select hla_swd
source [find target/at32f437xM.cfg]
reset_config none separate

33
cmake/at32-bootloader.cmake Normal file
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@ -0,0 +1,33 @@
main_sources(BOOTLOADER_SOURCES
common/log.c
common/log.h
common/printf.c
common/printf.h
common/string_light.c
common/string_light.h
common/typeconversion.c
common/typeconversion.h
drivers/bus.c
drivers/bus_busdev_i2c.c
drivers/bus_busdev_spi.c
drivers/bus_i2c_soft.c
drivers/io.c
drivers/light_led.c
drivers/persistent.c
drivers/rcc.c
drivers/serial.c
drivers/system.c
drivers/time.c
drivers/timer.c
drivers/flash_m25p16.c
drivers/flash_w25n01g.c
drivers/flash.c
fc/firmware_update_common.c
fc/firmware_update_common.h
target/common_hardware.c
)
list(APPEND BOOTLOADER_SOURCES ${MAIN_DIR}/src/bl/bl_main.c)

4
cmake/at32-stdperiph.cmake Normal file
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@ -0,0 +1,4 @@
main_sources(AT32_STDPERIPH_SRC
drivers/bus_spi_at32f43x.c
drivers/serial_uart_hal_at32f43x.c
)

430
cmake/at32.cmake Normal file
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@ -0,0 +1,430 @@
include(at32-bootloader)
include(at32f4)
include(CMakeParseArguments)
option(DEBUG_HARDFAULTS "Enable debugging of hard faults via custom handler")
option(SEMIHOSTING "Enable semihosting")
message("-- DEBUG_HARDFAULTS: ${DEBUG_HARDFAULTS}, SEMIHOSTING: ${SEMIHOSTING}")
set(CMSIS_DIR "${MAIN_LIB_DIR}/lib/main/AT32F43x/Drivers/CMSIS")
set(CMSIS_INCLUDE_DIR "${CMSIS_DIR}/cm4/core_support")
# DSP use common
set(CMSIS_DSP_DIR "${MAIN_LIB_DIR}/main/CMSIS/DSP")
set(CMSIS_DSP_INCLUDE_DIR "${CMSIS_DSP_DIR}/Include")
set(CMSIS_DSP_SRC
BasicMathFunctions/arm_mult_f32.c
TransformFunctions/arm_rfft_fast_f32.c
TransformFunctions/arm_cfft_f32.c
TransformFunctions/arm_rfft_fast_init_f32.c
TransformFunctions/arm_cfft_radix8_f32.c
TransformFunctions/arm_bitreversal2.S
CommonTables/arm_common_tables.c
ComplexMathFunctions/arm_cmplx_mag_f32.c
StatisticsFunctions/arm_max_f32.c
)
list(TRANSFORM CMSIS_DSP_SRC PREPEND "${CMSIS_DSP_DIR}/Source/")
set(AT32_STARTUP_DIR "${MAIN_SRC_DIR}/startup")
main_sources(AT32_VCP_SRC
drivers/serial_usb_vcp_at32f43x.c
drivers/usb_io.c
)
# SDCARD not supported yet
main_sources(AT32_SDCARD_SRC
drivers/sdcard/sdcard.c
drivers/sdcard/sdcard_spi.c
drivers/sdcard/sdcard_sdio.c
drivers/sdcard/sdcard_standard.c
)
# XXX: This code is not STM32 specific
main_sources(AT32_ASYNCFATFS_SRC
io/asyncfatfs/asyncfatfs.c
io/asyncfatfs/fat_standard.c
)
main_sources(AT32_MSC_SRC
msc/at32_msc_diskio.c
msc/emfat.c
msc/emfat_file.c
)
set(AT32_INCLUDE_DIRS
"${CMSIS_INCLUDE_DIR}"
"${CMSIS_DSP_INCLUDE_DIR}"
"${MAIN_SRC_DIR}/target"
)
set(AT32_DEFINITIONS
)
set(AT32_DEFAULT_HSE_MHZ 8)
set(AT32_LINKER_DIR "${MAIN_SRC_DIR}/target/link")
set(AT32_COMPILE_OPTIONS
-ffunction-sections
-fdata-sections
-fno-common
)
set(AT32_LINK_LIBRARIES
-lm
-lc
)
if(SEMIHOSTING)
list(APPEND AT32_LINK_LIBRARIES --specs=rdimon.specs -lrdimon)
list(APPEND AT32_DEFINITIONS SEMIHOSTING)
else()
list(APPEND AT32_LINK_LIBRARIES -lnosys)
endif()
set(AT32_LINK_OPTIONS
#-nostartfiles
--specs=nano.specs
-static
-Wl,-gc-sections
-Wl,-L${AT32_LINKER_DIR}
-Wl,--cref
-Wl,--no-wchar-size-warning
-Wl,--print-memory-usage
)
# Get target features
macro(get_at32_target_features output_var dir target_name)
execute_process(COMMAND "${CMAKE_C_COMPILER}" -E -dD -D${ARGV2} "${ARGV1}/target.h"
ERROR_VARIABLE _errors
RESULT_VARIABLE _result
OUTPUT_STRIP_TRAILING_WHITESPACE
OUTPUT_VARIABLE _contents)
if(NOT _result EQUAL 0)
message(FATAL_ERROR "error extracting features for AT32 target ${ARGV2}: ${_errors}")
endif()
string(REGEX MATCH "#define[\t ]+USE_VCP" HAS_VCP ${_contents})
if(HAS_VCP)
list(APPEND ${ARGV0} VCP)
endif()
string(REGEX MATCH "define[\t ]+USE_FLASHFS" HAS_FLASHFS ${_contents})
if(HAS_FLASHFS)
list(APPEND ${ARGV0} FLASHFS)
endif()
string(REGEX MATCH "define[\t ]+USE_SDCARD" HAS_SDCARD ${_contents})
if (HAS_SDCARD)
list(APPEND ${ARGV0} SDCARD)
string(REGEX MATCH "define[\t ]+USE_SDCARD_SDIO" HAS_SDIO ${_contents})
if (HAS_SDIO)
list(APPEND ${ARGV0} SDIO)
endif()
endif()
if(HAS_FLASHFS OR HAS_SDCARD)
list(APPEND ${ARGV0} MSC)
endif()
endmacro()
function(get_at32_flash_size out size)
# 4: 16, 6: 32, 8: 64, B: 128, C: 256, D: 384, E: 512, F: 768, G: 1024, H: 1536, I: 2048 KiB
string(TOUPPER ${size} s)
if(${s} STREQUAL "4")
set(${out} 16 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "6")
set(${out} 32 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "8")
set(${out} 64 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "8")
set(${out} 64 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "B")
set(${out} 128 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "C")
set(${out} 256 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "D")
set(${out} 384 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "E")
set(${out} 512 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "F")
set(${out} 768 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "G")
set(${out} 1024 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "H")
set(${out} 1536 PARENT_SCOPE)
return()
endif()
if(${s} STREQUAL "I")
set(${out} 2048 PARENT_SCOPE)
return()
endif()
endfunction()
function(add_hex_target name exe hex)
add_custom_target(${name} ALL
cmake -E env PATH="$ENV{PATH}"
# TODO: Overriding the start address with --set-start 0x08000000
# seems to be required due to some incorrect assumptions about .hex
# files in the configurator. Verify wether that's the case and fix
# the bug in configurator or delete this comment.
${CMAKE_OBJCOPY} -Oihex --set-start 0x08000000 $<TARGET_FILE:${exe}> ${hex}
BYPRODUCTS ${hex}
)
endfunction()
function(add_bin_target name exe bin)
add_custom_target(${name}
cmake -E env PATH="$ENV{PATH}"
${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${exe}> ${bin}
BYPRODUCTS ${bin}
)
endfunction()
function(generate_map_file target)
if(CMAKE_VERSION VERSION_LESS 3.15)
set(map "$<TARGET_FILE:${target}>.map")
else()
set(map "$<TARGET_FILE_DIR:${target}>/$<TARGET_FILE_BASE_NAME:${target}>.map")
endif()
target_link_options(${target} PRIVATE "-Wl,-Map,${map}")
endfunction()
function(set_linker_script target script)
set(script_path ${AT32_LINKER_DIR}/${args_LINKER_SCRIPT}.ld)
if(NOT EXISTS ${script_path})
message(FATAL_ERROR "linker script ${script_path} doesn't exist")
endif()
set_target_properties(${target} PROPERTIES LINK_DEPENDS ${script_path})
target_link_options(${elf_target} PRIVATE -T${script_path})
endfunction()
function(add_at32_executable)
cmake_parse_arguments(
args
# Boolean arguments
""
# Single value arguments
"FILENAME;NAME;OPTIMIZATION;OUTPUT_BIN_FILENAME;OUTPUT_HEX_FILENAME;OUTPUT_TARGET_NAME"
# Multi-value arguments
"COMPILE_DEFINITIONS;COMPILE_OPTIONS;INCLUDE_DIRECTORIES;LINK_OPTIONS;LINKER_SCRIPT;SOURCES"
# Start parsing after the known arguments
${ARGN}
)
set(elf_target ${args_NAME}.elf)
add_executable(${elf_target})
target_sources(${elf_target} PRIVATE ${args_SOURCES})
target_include_directories(${elf_target} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR} ${args_INCLUDE_DIRECTORIES} ${AT32_INCLUDE_DIRS})
target_compile_definitions(${elf_target} PRIVATE ${args_COMPILE_DEFINITIONS})
target_compile_options(${elf_target} PRIVATE ${AT32_COMPILE_OPTIONS} ${args_COMPILE_OPTIONS})
if(WARNINGS_AS_ERRORS)
target_compile_options(${elf_target} PRIVATE -Werror)
endif()
if (IS_RELEASE_BUILD)
target_compile_options(${elf_target} PRIVATE ${args_OPTIMIZATION})
target_link_options(${elf_target} PRIVATE ${args_OPTIMIZATION})
endif()
target_link_libraries(${elf_target} PRIVATE ${AT32_LINK_LIBRARIES})
target_link_options(${elf_target} PRIVATE ${AT32_LINK_OPTIONS} ${args_LINK_OPTIONS})
generate_map_file(${elf_target})
set_linker_script(${elf_target} ${args_LINKER_SCRIPT})
if(args_FILENAME)
set(basename ${CMAKE_BINARY_DIR}/${args_FILENAME})
set(hex_filename ${basename}.hex)
add_hex_target(${args_NAME} ${elf_target} ${hex_filename})
set(bin_filename ${basename}.bin)
add_bin_target(${args_NAME}.bin ${elf_target} ${bin_filename})
endif()
if(args_OUTPUT_BIN_FILENAME)
set(${args_OUTPUT_BIN_FILENAME} ${bin_filename} PARENT_SCOPE)
endif()
if(args_OUTPUT_TARGET_NAME)
set(${args_OUTPUT_TARGET_NAME} ${elf_target} PARENT_SCOPE)
endif()
if(args_OUTPUT_HEX_FILENAME)
set(${args_OUTPUT_HEX_FILENAME} ${hex_filename} PARENT_SCOPE)
endif()
endfunction()
# Main function of AT32
function(target_at32)
if(NOT arm-none-eabi STREQUAL TOOLCHAIN)
return()
endif()
# Parse keyword arguments
cmake_parse_arguments(
args
# Boolean arguments
"DISABLE_MSC;BOOTLOADER"
# Single value arguments
"HSE_MHZ;LINKER_SCRIPT;NAME;OPENOCD_TARGET;OPTIMIZATION;STARTUP;SVD"
# Multi-value arguments
"COMPILE_DEFINITIONS;COMPILE_OPTIONS;INCLUDE_DIRECTORIES;LINK_OPTIONS;SOURCES;MSC_SOURCES;MSC_INCLUDE_DIRECTORIES;VCP_SOURCES;VCP_INCLUDE_DIRECTORIES"
# Start parsing after the known arguments
${ARGN}
)
set(name ${args_NAME})
if (args_HSE_MHZ)
set(hse_mhz ${args_HSE_MHZ})
else()
set(hse_mhz ${AT32_DEFAULT_HSE_MHZ})
endif()
set(target_sources ${AT32_STARTUP_DIR}/${args_STARTUP})
list(APPEND target_sources ${args_SOURCES})
file(GLOB target_c_sources "${CMAKE_CURRENT_SOURCE_DIR}/*.c")
file(GLOB target_h_sources "${CMAKE_CURRENT_SOURCE_DIR}/*.h")
list(APPEND target_sources ${target_c_sources} ${target_h_sources})
set(target_include_directories ${args_INCLUDE_DIRECTORIES})
set(target_definitions ${AT32_DEFINITIONS} ${COMMON_COMPILE_DEFINITIONS})
get_at32_target_features(features "${CMAKE_CURRENT_SOURCE_DIR}" ${name})
set_property(TARGET ${elf_target} PROPERTY FEATURES ${features})
if(VCP IN_LIST features)
list(APPEND target_sources ${AT32_VCP_SRC} ${args_VCP_SOURCES})
list(APPEND target_include_directories ${args_VCP_INCLUDE_DIRECTORIES})
endif()
if(SDCARD IN_LIST features)
list(APPEND target_sources ${AT32_SDCARD_SRC} ${AT32_ASYNCFATFS_SRC})
endif()
set(msc_sources)
if(NOT args_DISABLE_MSC AND MSC IN_LIST features)
list(APPEND target_include_directories ${args_MSC_INCLUDE_DIRECTORIES})
list(APPEND msc_sources ${AT32_MSC_SRC} ${args_MSC_SOURCES})
list(APPEND target_definitions USE_USB_MSC)
if(FLASHFS IN_LIST features)
list(APPEND msc_sources ${AT32_MSC_FLASH_SRC})
endif()
if (SDCARD IN_LIST features)
list(APPEND msc_sources ${AT32_MSC_SDCARD_SRC})
endif()
endif()
math(EXPR hse_value "${hse_mhz} * 1000000")
list(APPEND target_definitions "HSE_VALUE=${hse_value}")
if(args_COMPILE_DEFINITIONS)
list(APPEND target_definitions ${args_COMPILE_DEFINITIONS})
endif()
if(DEBUG_HARDFAULTS)
list(APPEND target_definitions DEBUG_HARDFAULTS)
endif()
string(TOLOWER ${PROJECT_NAME} lowercase_project_name)
set(binary_name ${lowercase_project_name}_${FIRMWARE_VERSION}_${name})
if(DEFINED BUILD_SUFFIX AND NOT "" STREQUAL "${BUILD_SUFFIX}")
set(binary_name "${binary_name}_${BUILD_SUFFIX}")
endif()
# Main firmware
add_at32_executable(
NAME ${name}
FILENAME ${binary_name}
SOURCES ${target_sources} ${msc_sources} ${CMSIS_DSP_SRC} ${COMMON_SRC}
COMPILE_DEFINITIONS ${target_definitions}
COMPILE_OPTIONS ${args_COMPILE_OPTIONS}
INCLUDE_DIRECTORIES ${target_include_directories}
LINK_OPTIONS ${args_LINK_OPTIONS}
LINKER_SCRIPT ${args_LINKER_SCRIPT}
OPTIMIZATION ${args_OPTIMIZATION}
OUTPUT_BIN_FILENAME main_bin_filename
OUTPUT_HEX_FILENAME main_hex_filename
OUTPUT_TARGET_NAME main_target_name
)
set_property(TARGET ${main_target_name} PROPERTY OPENOCD_TARGET ${args_OPENOCD_TARGET})
set_property(TARGET ${main_target_name} PROPERTY OPENOCD_DEFAULT_INTERFACE atlink)
set_property(TARGET ${main_target_name} PROPERTY SVD ${args_SVD})
setup_firmware_target(${main_target_name} ${name} ${ARGN})
if(args_BOOTLOADER)
# Bootloader for the target
set(bl_suffix _bl)
add_at32_executable(
NAME ${name}${bl_suffix}
FILENAME ${binary_name}${bl_suffix}
SOURCES ${target_sources} ${BOOTLOADER_SOURCES}
COMPILE_DEFINITIONS ${target_definitions} BOOTLOADER MSP_FIRMWARE_UPDATE
COMPILE_OPTIONS ${args_COMPILE_OPTIONS}
INCLUDE_DIRECTORIES ${target_include_directories}
LINK_OPTIONS ${args_LINK_OPTIONS}
LINKER_SCRIPT ${args_LINKER_SCRIPT}${bl_suffix}
OPTIMIZATION ${args_OPTIMIZATION}
OUTPUT_BIN_FILENAME bl_bin_filename
OUTPUT_HEX_FILENAME bl_hex_filename
OUTPUT_TARGET_NAME bl_target_name
)
setup_executable(${bl_target_name} ${name})
# Main firmware, but for running with the bootloader
set(for_bl_suffix _for_bl)
add_at32_executable(
NAME ${name}${for_bl_suffix}
FILENAME ${binary_name}${for_bl_suffix}
SOURCES ${target_sources} ${msc_sources} ${CMSIS_DSP_SRC} ${COMMON_SRC}
COMPILE_DEFINITIONS ${target_definitions} MSP_FIRMWARE_UPDATE
COMPILE_OPTIONS ${args_COMPILE_OPTIONS}
INCLUDE_DIRECTORIES ${target_include_directories}
LINK_OPTIONS ${args_LINK_OPTIONS}
LINKER_SCRIPT ${args_LINKER_SCRIPT}${for_bl_suffix}
OPTIMIZATION ${args_OPTIMIZATION}
OUTPUT_BIN_FILENAME for_bl_bin_filename
OUTPUT_HEX_FILENAME for_bl_hex_filename
OUTPUT_TARGET_NAME for_bl_target_name
)
setup_executable(${for_bl_target_name} ${name})
# Combined with bootloader and main firmware
set(with_bl_suffix _with_bl)
set(combined_hex ${CMAKE_BINARY_DIR}/${binary_name}${with_bl_suffix}.hex)
set(with_bl_target ${name}${with_bl_suffix})
add_custom_target(${with_bl_target}
${CMAKE_SOURCE_DIR}/src/utils/combine_tool ${bl_bin_filename} ${for_bl_bin_filename} ${combined_hex}
BYPRODUCTS ${combined_hex}
)
add_dependencies(${with_bl_target} ${bl_target_name} ${for_bl_target_name})
endif()
# clean_<target>
set(generator_cmd "")
if (CMAKE_GENERATOR STREQUAL "Unix Makefiles")
set(generator_cmd "make")
elseif(CMAKE_GENERATOR STREQUAL "Ninja")
set(generator_cmd "ninja")
endif()
if (NOT generator_cmd STREQUAL "")
set(clean_target "clean_${name}")
add_custom_target(${clean_target}
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
COMMAND ${generator_cmd} clean
COMMENT "Removing intermediate files for ${name}")
set_property(TARGET ${clean_target} PROPERTY
EXCLUDE_FROM_ALL 1
EXCLUDE_FROM_DEFAULT_BUILD 1)
endif()
endfunction()

45
cmake/at32f4-usb.cmake Normal file
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@ -0,0 +1,45 @@
set(AT32_USBCORE_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Middlewares/AT/AT32_USB_Device_Library/Core")
set(AT32_USBCDC_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Middlewares/AT/AT32_USB_Device_Library/Class/usbd_class/cdc")
set(AT32_USBMSC_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Middlewares/AT/AT32_USB_Device_Library/Class/usbd_class/msc")
set(AT32F4_USB_INCLUDE_DIRS
"${AT32_USBCORE_DIR}/Inc"
"${AT32_USBCDC_DIR}"
"${AT32_USBMSC_DIR}"
)
set(AT32_USBCORE_SRC
usb_core.c
usbd_core.c
usbd_int.c
usbd_sdr.c
)
list(TRANSFORM AT32_USBCORE_SRC PREPEND "${AT32_USBCORE_DIR}/Src/")
set(AT32_USBCDC_SRC
"${AT32_USBCDC_DIR}/cdc_class.c"
"${AT32_USBCDC_DIR}/cdc_desc.c"
)
main_sources(AT32F4_VCP_SRC
drivers/serial_usb_vcp_at32f43x.c
drivers/usb_io.c
)
set(AT32F4_USBMSC_SRC
msc_desc.c
msc_class.c
msc_bot_scsi.c
)
main_sources(AT32F4_MSC_SRC
drivers/usb_msc_at32f43x.c
)
list(TRANSFORM AT32F4_USBMSC_SRC PREPEND "${AT32_USBMSC_DIR}/")
list(APPEND AT32F4_USBMSC_SRC ${AT32F4_MSC_SRC})
list(APPEND AT32F4_USB_SRC ${AT32F4_VCP_SRC})
list(APPEND AT32F4_USB_SRC ${AT32_USBCORE_SRC})
list(APPEND AT32F4_USB_SRC ${AT32_USBCDC_SRC})

114
cmake/at32f4.cmake Normal file
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@ -0,0 +1,114 @@
include(cortex-m4f)
include(at32-stdperiph)
include(at32f4-usb)
set(AT32F4_STDPERIPH_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver")
set(AT32F4_CMSIS_DEVICE_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Drivers/CMSIS/Device/ST/AT32F43x")
set(AT32F4_CMSIS_DRIVERS_DIR "${MAIN_LIB_DIR}/main/AT32F43x/Drivers/CMSIS")
set(AT32F4_STDPERIPH_SRC_EXCLUDES
at32f435_437_can.c
at32f435_437_dvp.c
at32f435_437_emac
at32f435_437_xmc.c
)
set(AT32F4_STDPERIPH_SRC_DIR "${AT32F4_STDPERIPH_DIR}/src")
glob_except(AT32F4_STDPERIPH_SRC "${AT32F4_STDPERIPH_SRC_DIR}/*.c" "${AT32F4_STDPERIPH_SRC_EXCLUDES}")
list(APPEND AT32F4_STDPERIPH_SRC "${AT32F4_CMSIS_DEVICE_DIR}/at32f435_437_clock.c" )
main_sources(AT32F4_SRC
target/system_at32f435_437.c
config/config_streamer_at32f43x.c
config/config_streamer_ram.c
config/config_streamer_extflash.c
drivers/adc_at32f43x.c
drivers/i2c_application.c
drivers/bus_i2c_at32f43x.c
drivers/bus_spi_at32f43x
drivers/serial_uart_hal_at32f43x.c
drivers/serial_uart_at32f43x.c
drivers/system_at32f43x.c
drivers/timer.c
drivers/timer_impl_stdperiph_at32.c
drivers/timer_at32f43x.c
drivers/uart_inverter.c
drivers/dma_at32f43x.c
)
set(AT32F4_INCLUDE_DIRS
${CMSIS_INCLUDE_DIR}
${CMSIS_DSP_INCLUDE_DIR}
${AT32F4_CMSIS_DRIVERS_DIR}
${AT32F4_STDPERIPH_DIR}/inc
${AT32F4_CMSIS_DEVICE_DIR}
#"${AT32F4_I2C_DIR}"
)
set(AT32F4_DEFINITIONS
${CORTEX_M4F_DEFINITIONS}
AT32F43x
USE_STDPERIPH_DRIVER
)
function(target_at32f43x)
target_at32(
SOURCES ${AT32_STDPERIPH_SRC} ${AT32F4_SRC}
COMPILE_DEFINITIONS ${AT32F4_DEFINITIONS}
COMPILE_OPTIONS ${CORTEX_M4F_COMMON_OPTIONS} ${CORTEX_M4F_COMPILE_OPTIONS}
INCLUDE_DIRECTORIES ${AT32F4_INCLUDE_DIRS}
LINK_OPTIONS ${CORTEX_M4F_COMMON_OPTIONS} ${CORTEX_M4F_LINK_OPTIONS}
MSC_SOURCES ${AT32F4_USBMSC_SRC} ${AT32F4_MSC_SRC}
VCP_SOURCES ${AT32F4_USB_SRC} ${AT32F4_VCP_SRC}
VCP_INCLUDE_DIRECTORIES ${AT32F4_USB_INCLUDE_DIRS}
OPTIMIZATION -O2
OPENOCD_TARGET at32f437xx
${ARGN}
)
endfunction()
#target_at32f43x_xMT7
#target_at32f43x_xGT7
set(at32f43x_xMT7_COMPILE_DEFINITIONS
AT32F437VMT7
MCU_FLASH_SIZE=4032
)
function(target_at32f43x_xMT7 name)
target_at32f43x(
NAME ${name}
STARTUP startup_at32f435_437.s
SOURCES ${AT32F4_STDPERIPH_SRC}
COMPILE_DEFINITIONS ${at32f43x_xMT7_COMPILE_DEFINITIONS}
LINKER_SCRIPT at32_flash_f43xM
#BOOTLOADER
SVD at32f43x_xMT7
${ARGN}
)
endfunction()
set(at32f43x_xGT7_COMPILE_DEFINITIONS
AT32F435RGT7
MCU_FLASH_SIZE=1024
)
function(target_at32f43x_xGT7 name)
target_at32f43x(
NAME ${name}
STARTUP startup_at32f435_437.s
SOURCES ${AT32F4_STDPERIPH_SRC}
COMPILE_DEFINITIONS ${at32f43x_xGT7_COMPILE_DEFINITIONS}
LINKER_SCRIPT at32_flash_f43xG
#BOOTLOADER
SVD at32f43x_xGT7
${ARGN}
)
endfunction()

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/**
**************************************************************************
* @file at32f435_437_acc.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 acc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_ACC_H
#define __AT32F435_437_ACC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup ACC
* @{
*/
/** @defgroup ACC_exported_constants
* @{
*/
#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
#define ACC_SOF_OTG1 ((uint16_t)0x0000) /*!< acc sof signal select: otg1 */
#define ACC_SOF_OTG2 ((uint16_t)0x0004) /*!< acc sof signal select: otg2 */
/**
* @}
*/
/** @defgroup ACC_exported_types
* @{
*/
/**
* @brief type define acc register all
*/
typedef struct
{
/**
* @brief acc sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t calrdy : 1; /* [0] */
__IO uint32_t rslost : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
/**
* @brief acc ctrl1 register, offset:0x04
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t calon : 1; /* [0] */
__IO uint32_t entrim : 1; /* [1] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t eien : 1; /* [4] */
__IO uint32_t calrdyien : 1; /* [5] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t step : 4; /* [11:8] */
__IO uint32_t reserved3 : 20;/* [31:12] */
} ctrl1_bit;
};
/**
* @brief acc ctrl2 register, offset:0x08
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t hickcal : 8; /* [7:0] */
__IO uint32_t hicktrim : 6; /* [13:8] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} ctrl2_bit;
};
/**
* @brief acc acc_c1 register, offset:0x0C
*/
union
{
__IO uint32_t c1;
struct
{
__IO uint32_t c1 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c1_bit;
};
/**
* @brief acc acc_c2 register, offset:0x10
*/
union
{
__IO uint32_t c2;
struct
{
__IO uint32_t c2 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c2_bit;
};
/**
* @brief acc acc_c3 register, offset:0x14
*/
union
{
__IO uint32_t c3;
struct
{
__IO uint32_t c3 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c3_bit;
};
} acc_type;
/**
* @}
*/
#define ACC ((acc_type *) ACC_BASE)
/** @defgroup ACC_exported_functions
* @{
*/
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
void acc_step_set(uint8_t step_value);
void acc_sof_select(uint16_t sof_sel);
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
uint8_t acc_hicktrim_get(void);
uint8_t acc_hickcal_get(void);
void acc_write_c1(uint16_t acc_c1_value);
void acc_write_c2(uint16_t acc_c2_value);
void acc_write_c3(uint16_t acc_c3_value);
uint16_t acc_read_c1(void);
uint16_t acc_read_c2(void);
uint16_t acc_read_c3(void);
flag_status acc_flag_get(uint16_t acc_flag);
void acc_flag_clear(uint16_t acc_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_adc.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 adc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_ADC_H
#define __AT32F435_437_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_interrupts_definition
* @brief adc interrupt
* @{
*/
#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @brief adc flag
* @{
*/
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
/**
* @}
*/
/** @defgroup ADC_exported_types
* @{
*/
/**
* @brief adc division type
*/
typedef enum
{
ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
} adc_div_type;
/**
* @brief adc combine mode type
*/
typedef enum
{
ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15, /*!< double slaver preempt simultaneous mode only */
ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16, /*!< double slaver ordinary simultaneous mode only */
ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17, /*!< double slaver ordinary shifting mode only */
ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19 /*!< double slaver preempt interleaved trigger mode only */
} adc_combine_mode_type;
/**
* @brief adc common dma mode type
*/
typedef enum
{
ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
ADC_COMMON_DMAMODE_4 = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
ADC_COMMON_DMAMODE_5 = 0x05 /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
} adc_common_dma_mode_type;
/**
* @brief adc common sampling interval type
*/
typedef enum
{
ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
} adc_sampling_interval_type;
/**
* @brief adc conversion resolution type
*/
typedef enum
{
ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
} adc_resolution_type;
/**
* @brief adc data align type
*/
typedef enum
{
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
} adc_data_align_type;
/**
* @brief adc channel select type
*/
typedef enum
{
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
} adc_channel_select_type;
/**
* @brief adc sampletime select type
*/
typedef enum
{
ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
} adc_sampletime_select_type;
/**
* @brief adc ordinary group trigger event select type
*/
typedef enum
{
ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR20CH1 = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR20CH2 = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR20CH3 = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
} adc_ordinary_trig_select_type;
/**
* @brief adc ordinary channel conversion's external_trigger_edge type
*/
typedef enum
{
ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
} adc_ordinary_trig_edge_type;
/**
* @brief adc preempt group external trigger event select type
*/
typedef enum
{
ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR20CH4 = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
} adc_preempt_trig_select_type;
/**
* @brief adc preempt channel conversion's external_trigger_edge type
*/
typedef enum
{
ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
} adc_preempt_trig_edge_type;
/**
* @brief adc preempt channel type
*/
typedef enum
{
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
} adc_preempt_channel_type;
/**
* @brief adc voltage_monitoring type
*/
typedef enum
{
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
} adc_voltage_monitoring_type;
/**
* @brief adc oversample ratio type
*/
typedef enum
{
ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
} adc_oversample_ratio_type;
/**
* @brief adc oversample shift type
*/
typedef enum
{
ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
} adc_oversample_shift_type;
/**
* @brief adc ordinary oversample recover type
*/
typedef enum
{
ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
} adc_ordinary_oversample_restart_type;
/**
* @brief adc common config type
*/
typedef struct
{
adc_combine_mode_type combine_mode; /*!< adc combine mode select */
adc_div_type div; /*!< adc division select */
adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
confirm_state vbat_state; /*!< adc voltage battery state */
} adc_common_config_type;
/**
* @brief adc base config type
*/
typedef struct
{
confirm_state sequence_mode; /*!< adc sequence mode */
confirm_state repeat_mode; /*!< adc repeat mode */
adc_data_align_type data_align; /*!< adc data alignment */
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
} adc_base_config_type;
/**
* @brief type define adc register all
*/
typedef struct
{
/**
* @brief adc sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t vmor : 1; /* [0] */
__IO uint32_t occe : 1; /* [1] */
__IO uint32_t pcce : 1; /* [2] */
__IO uint32_t pccs : 1; /* [3] */
__IO uint32_t occs : 1; /* [4] */
__IO uint32_t occo : 1; /* [5] */
__IO uint32_t rdy : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} sts_bit;
};
/**
* @brief adc ctrl1 register, offset:0x04
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t vmcsel : 5; /* [4:0] */
__IO uint32_t occeien : 1; /* [5] */
__IO uint32_t vmorien : 1; /* [6] */
__IO uint32_t pcceien : 1; /* [7] */
__IO uint32_t sqen : 1; /* [8] */
__IO uint32_t vmsgen : 1; /* [9] */
__IO uint32_t pcautoen : 1; /* [10] */
__IO uint32_t ocpen : 1; /* [11] */
__IO uint32_t pcpen : 1; /* [12] */
__IO uint32_t ocpcnt : 3; /* [15:13] */
__IO uint32_t reserved1 : 6; /* [21:16] */
__IO uint32_t pcvmen : 1; /* [22] */
__IO uint32_t ocvmen : 1; /* [23] */
__IO uint32_t crsel : 2; /* [25:24] */
__IO uint32_t occoien : 1; /* [26] */
__IO uint32_t reserved2 : 5; /* [31:27] */
} ctrl1_bit;
};
/**
* @brief adc ctrl2 register, offset:0x08
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t adcen : 1; /* [0] */
__IO uint32_t rpen : 1; /* [1] */
__IO uint32_t adcal : 1; /* [2] */
__IO uint32_t adcalinit : 1; /* [3] */
__IO uint32_t adabrt : 1; /* [4] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t ocdmaen : 1; /* [8] */
__IO uint32_t ocdrcen : 1; /* [9] */
__IO uint32_t eocsfen : 1; /* [10] */
__IO uint32_t dtalign : 1; /* [11] */
__IO uint32_t reserved2 : 4; /* [15:12] */
__IO uint32_t pctesel_l : 4; /* [19:16] */
__IO uint32_t pcete : 2; /* [21:20] */
__IO uint32_t pcswtrg : 1; /* [22] */
__IO uint32_t pctesel_h : 1; /* [23] */
__IO uint32_t octesel_l : 4; /* [27:24] */
__IO uint32_t ocete : 2; /* [29:28] */
__IO uint32_t ocswtrg : 1; /* [30] */
__IO uint32_t octesel_h : 1; /* [31] */
} ctrl2_bit;
};
/**
* @brief adc spt1 register, offset:0x0C
*/
union
{
__IO uint32_t spt1;
struct
{
__IO uint32_t cspt10 : 3; /* [2:0] */
__IO uint32_t cspt11 : 3; /* [5:3] */
__IO uint32_t cspt12 : 3; /* [8:6] */
__IO uint32_t cspt13 : 3; /* [11:9] */
__IO uint32_t cspt14 : 3; /* [14:12] */
__IO uint32_t cspt15 : 3; /* [17:15] */
__IO uint32_t cspt16 : 3; /* [20:18] */
__IO uint32_t cspt17 : 3; /* [23:21] */
__IO uint32_t cspt18 : 3; /* [26:24] */
__IO uint32_t reserved1 : 5;/* [31:27] */
} spt1_bit;
};
/**
* @brief adc spt2 register, offset:0x10
*/
union
{
__IO uint32_t spt2;
struct
{
__IO uint32_t cspt0 : 3;/* [2:0] */
__IO uint32_t cspt1 : 3;/* [5:3] */
__IO uint32_t cspt2 : 3;/* [8:6] */
__IO uint32_t cspt3 : 3;/* [11:9] */
__IO uint32_t cspt4 : 3;/* [14:12] */
__IO uint32_t cspt5 : 3;/* [17:15] */
__IO uint32_t cspt6 : 3;/* [20:18] */
__IO uint32_t cspt7 : 3;/* [23:21] */
__IO uint32_t cspt8 : 3;/* [26:24] */
__IO uint32_t cspt9 : 3;/* [29:27] */
__IO uint32_t reserved1 : 2;/* [31:30] */
} spt2_bit;
};
/**
* @brief adc pcdto1 register, offset:0x14
*/
union
{
__IO uint32_t pcdto1;
struct
{
__IO uint32_t pcdto1 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto1_bit;
};
/**
* @brief adc pcdto2 register, offset:0x18
*/
union
{
__IO uint32_t pcdto2;
struct
{
__IO uint32_t pcdto2 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto2_bit;
};
/**
* @brief adc pcdto3 register, offset:0x1C
*/
union
{
__IO uint32_t pcdto3;
struct
{
__IO uint32_t pcdto3 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto3_bit;
};
/**
* @brief adc pcdto4 register, offset:0x20
*/
union
{
__IO uint32_t pcdto4;
struct
{
__IO uint32_t pcdto4 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto4_bit;
};
/**
* @brief adc vmhb register, offset:0x24
*/
union
{
__IO uint32_t vmhb;
struct
{
__IO uint32_t vmhb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmhb_bit;
};
/**
* @brief adc vmlb register, offset:0x28
*/
union
{
__IO uint32_t vmlb;
struct
{
__IO uint32_t vmlb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmlb_bit;
};
/**
* @brief adc osq1 register, offset:0x2C
*/
union
{
__IO uint32_t osq1;
struct
{
__IO uint32_t osn13 : 5; /* [4:0] */
__IO uint32_t osn14 : 5; /* [9:5] */
__IO uint32_t osn15 : 5; /* [14:10] */
__IO uint32_t osn16 : 5; /* [19:15] */
__IO uint32_t oclen : 4; /* [23:20] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} osq1_bit;
};
/**
* @brief adc osq2 register, offset:0x30
*/
union
{
__IO uint32_t osq2;
struct
{
__IO uint32_t osn7 : 5; /* [4:0] */
__IO uint32_t osn8 : 5; /* [9:5] */
__IO uint32_t osn9 : 5; /* [14:10] */
__IO uint32_t osn10 : 5; /* [19:15] */
__IO uint32_t osn11 : 5; /* [24:20] */
__IO uint32_t osn12 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq2_bit;
};
/**
* @brief adc osq3 register, offset:0x34
*/
union
{
__IO uint32_t osq3;
struct
{
__IO uint32_t osn1 : 5; /* [4:0] */
__IO uint32_t osn2 : 5; /* [9:5] */
__IO uint32_t osn3 : 5; /* [14:10] */
__IO uint32_t osn4 : 5; /* [19:15] */
__IO uint32_t osn5 : 5; /* [24:20] */
__IO uint32_t osn6 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq3_bit;
};
/**
* @brief adc psq register, offset:0x38
*/
union
{
__IO uint32_t psq;
struct
{
__IO uint32_t psn1 : 5; /* [4:0] */
__IO uint32_t psn2 : 5; /* [9:5] */
__IO uint32_t psn3 : 5; /* [14:10] */
__IO uint32_t psn4 : 5; /* [19:15] */
__IO uint32_t pclen : 2; /* [21:20] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} psq_bit;
};
/**
* @brief adc pdt1 register, offset:0x3C
*/
union
{
__IO uint32_t pdt1;
struct
{
__IO uint32_t pdt1 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt1_bit;
};
/**
* @brief adc pdt2 register, offset:0x40
*/
union
{
__IO uint32_t pdt2;
struct
{
__IO uint32_t pdt2 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt2_bit;
};
/**
* @brief adc pdt3 register, offset:0x44
*/
union
{
__IO uint32_t pdt3;
struct
{
__IO uint32_t pdt3 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt3_bit;
};
/**
* @brief adc pdt4 register, offset:0x48
*/
union
{
__IO uint32_t pdt4;
struct
{
__IO uint32_t pdt4 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt4_bit;
};
/**
* @brief adc odt register, offset:0x4C
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} odt_bit;
};
__IO uint32_t reserved1[12];
/**
* @brief adc ovsp register, offset:0x80
*/
union
{
__IO uint32_t ovsp;
struct
{
__IO uint32_t oosen : 1; /* [0] */
__IO uint32_t posen : 1; /* [1] */
__IO uint32_t osrsel : 3; /* [4:2] */
__IO uint32_t osssel : 4; /* [8:5] */
__IO uint32_t oostren : 1; /* [9] */
__IO uint32_t oosrsel : 1; /* [10] */
__IO uint32_t reserved1 : 21; /* [31:11] */
} ovsp_bit;
};
__IO uint32_t reserved2[12];
/**
* @brief adc calval register, offset:0xB4
*/
union
{
__IO uint32_t calval;
struct
{
__IO uint32_t calval : 7; /* [6:0] */
__IO uint32_t reserved1 : 25; /* [31:7] */
} calval_bit;
};
} adc_type;
/**
* @brief type define adc register all
*/
typedef struct
{
/**
* @brief adc csts register, offset:0x00
*/
union
{
__IO uint32_t csts;
struct
{
__IO uint32_t vmor1 : 1; /* [0] */
__IO uint32_t occe1 : 1; /* [1] */
__IO uint32_t pcce1 : 1; /* [2] */
__IO uint32_t pccs1 : 1; /* [3] */
__IO uint32_t occs1 : 1; /* [4] */
__IO uint32_t occo1 : 1; /* [5] */
__IO uint32_t rdy1 : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t vmor2 : 1; /* [8] */
__IO uint32_t occe2 : 1; /* [9] */
__IO uint32_t pcce2 : 1; /* [10] */
__IO uint32_t pccs2 : 1; /* [11] */
__IO uint32_t occs2 : 1; /* [12] */
__IO uint32_t occo2 : 1; /* [13] */
__IO uint32_t rdy2 : 1; /* [14] */
__IO uint32_t reserved2 : 1; /* [15] */
__IO uint32_t vmor3 : 1; /* [16] */
__IO uint32_t occe3 : 1; /* [17] */
__IO uint32_t pcce3 : 1; /* [18] */
__IO uint32_t pccs3 : 1; /* [19] */
__IO uint32_t occs3 : 1; /* [20] */
__IO uint32_t occo3 : 1; /* [21] */
__IO uint32_t rdy3 : 1; /* [22] */
__IO uint32_t reserved3 : 9; /* [31:23] */
} csts_bit;
};
/**
* @brief adc cctrl register, offset:0x04
*/
union
{
__IO uint32_t cctrl;
struct
{
__IO uint32_t mssel : 5; /* [4_0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t asisel : 4; /* [11:8] */
__IO uint32_t reserved2 : 1; /* [12] */
__IO uint32_t msdrcen : 1; /* [13] */
__IO uint32_t msdmasel_l : 2; /* [15:14] */
__IO uint32_t adcdiv : 4; /* [19:16] */
__IO uint32_t reserved3 : 2; /* [21:20] */
__IO uint32_t vbaten : 1; /* [22] */
__IO uint32_t itsrven : 1; /* [23] */
__IO uint32_t reserved4 : 4; /* [27:24] */
__IO uint32_t msdmasel_h : 1; /* [28] */
__IO uint32_t reserved5 : 3; /* [31:29] */
} cctrl_bit;
};
/**
* @brief adc codt register, offset:0x08
*/
union
{
__IO uint32_t codt;
struct
{
__IO uint32_t codtl : 16; /* [15:0] */
__IO uint32_t codth : 16; /* [31:16] */
} codt_bit;
};
} adccom_type;
/**
* @}
*/
#define ADC1 ((adc_type *) ADC1_BASE)
#define ADC2 ((adc_type *) ADC2_BASE)
#define ADC3 ((adc_type *) ADC3_BASE)
#define ADCCOM ((adccom_type *) ADCCOM_BASE)
/** @defgroup ADC_exported_functions
* @{
*/
void adc_reset(void);
void adc_enable(adc_type *adc_x, confirm_state new_state);
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
void adc_common_config(adc_common_config_type *adc_common_struct);
void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
void adc_voltage_battery_enable(confirm_state new_state);
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
void adc_calibration_init(adc_type *adc_x);
flag_status adc_calibration_init_status_get(adc_type *adc_x);
void adc_calibration_start(adc_type *adc_x);
flag_status adc_calibration_status_get(adc_type *adc_x);
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_conversion_stop(adc_type *adc_x);
flag_status adc_conversion_stop_status_get(adc_type *adc_x);
void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint32_t adc_combine_ordinary_conversion_data_get(void);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_crc.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 crc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CRC_H
#define __AT32F435_437_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_exported_types
* @{
*/
/**
* @brief crc reverse input data
*/
typedef enum
{
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
} crc_reverse_input_type;
/**
* @brief crc reverse output data
*/
typedef enum
{
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief type define crc register all
*/
typedef struct
{
/**
* @brief crc dt register, offset:0x00
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 32; /* [31:0] */
} dt_bit;
};
/**
* @brief crc cdt register, offset:0x04
*/
union
{
__IO uint32_t cdt;
struct
{
__IO uint32_t cdt : 8 ; /* [7:0] */
__IO uint32_t reserved1 : 24 ;/* [31:8] */
} cdt_bit;
};
/**
* @brief crc ctrl register, offset:0x08
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 4 ; /* [4:1] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
} ctrl_bit;
};
/**
* @brief crm reserved1 register, offset:0x0C
*/
__IO uint32_t reserved1;
/**
* @brief crc idt register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt : 32; /* [31:0] */
} idt_bit;
};
} crc_type;
/**
* @}
*/
#define CRC ((crc_type *) CRC_BASE)
/** @defgroup CRC_exported_functions
* @{
*/
void crc_data_reset(void);
uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_dac.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dac header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_DAC_H
#define __AT32F435_437_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup DAC
* @{
*/
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
/** @defgroup DAC_exported_types
* @{
*/
/**
* @brief dac select type
*/
typedef enum
{
DAC1_SELECT = 0x01, /*!< dac1 select */
DAC2_SELECT = 0x02 /*!< dac2 select */
} dac_select_type;
/**
* @brief dac trigger type
*/
typedef enum
{
DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
} dac_trigger_type;
/**
* @brief dac wave type
*/
typedef enum
{
DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
} dac_wave_type;
/**
* @brief dac mask amplitude type
*/
typedef enum
{
DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
} dac_mask_amplitude_type;
/**
* @brief dac1 aligned data type
*/
typedef enum
{
DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
} dac1_aligned_data_type;
/**
* @brief dac2 aligned data type
*/
typedef enum
{
DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
} dac2_aligned_data_type;
/**
* @brief dac dual data type
*/
typedef enum
{
DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
} dac_dual_data_type;
/**
* @brief type define dac register all
*/
typedef struct
{
/**
* @brief dac ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t d1en : 1; /* [0] */
__IO uint32_t d1obdis : 1; /* [1] */
__IO uint32_t d1trgen : 1; /* [2] */
__IO uint32_t d1trgsel : 3; /* [5:3] */
__IO uint32_t d1nm : 2; /* [7:6] */
__IO uint32_t d1nbsel : 4; /* [11:8] */
__IO uint32_t d1dmaen : 1; /* [12] */
__IO uint32_t d1dmaudrien : 1; /* [13] */
__IO uint32_t reserved1 : 2; /* [15:14] */
__IO uint32_t d2en : 1; /* [16] */
__IO uint32_t d2obdis : 1; /* [17] */
__IO uint32_t d2trgen : 1; /* [18] */
__IO uint32_t d2trgsel : 3; /* [21:19] */
__IO uint32_t d2nm : 2; /* [23:22] */
__IO uint32_t d2nbsel : 4; /* [27:24] */
__IO uint32_t d2dmaen : 1; /* [28] */
__IO uint32_t d2dmaudrien : 1; /* [29] */
__IO uint32_t reserved2 : 2; /* [31:30] */
} ctrl_bit;
};
/**
* @brief dac swtrg register, offset:0x04
*/
union
{
__IO uint32_t swtrg;
struct
{
__IO uint32_t d1swtrg : 1; /* [0] */
__IO uint32_t d2swtrg : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} swtrg_bit;
};
/**
* @brief dac d1dth12r register, offset:0x08
*/
union
{
__IO uint32_t d1dth12r;
struct
{
__IO uint32_t d1dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d1dth12r_bit;
};
/**
* @brief dac d1dth12l register, offset:0x0C
*/
union
{
__IO uint32_t d1dth12l;
struct
{
__IO uint32_t d1dt12l : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d1dth12l_bit;
};
/**
* @brief dac d1dth8r register, offset:0x10
*/
union
{
__IO uint32_t d1dth8r;
struct
{
__IO uint32_t d1dt8r : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} d1dth8r_bit;
};
/**
* @brief dac d2dth12r register, offset:0x14
*/
union
{
__IO uint32_t d2dth12r;
struct
{
__IO uint32_t d2dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d2dth12r_bit;
};
/**
* @brief dac d2dth12l register, offset:0x18
*/
union
{
__IO uint32_t d2dth12l;
struct
{
__IO uint32_t d2dt12l : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:2] */
} d2dth12l_bit;
};
/**
* @brief dac d2dth8r register, offset:0x1C
*/
union
{
__IO uint32_t d2dth8r;
struct
{
__IO uint32_t d2dt8r : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} d2dth8r_bit;
};
/**
* @brief dac ddth12r register, offset:0x20
*/
union
{
__IO uint32_t ddth12r;
struct
{
__IO uint32_t dd1dt12r : 12;/* [11:0] */
__IO uint32_t reserved1 : 4; /* [15:12] */
__IO uint32_t dd2dt12r : 12;/* [27:16] */
__IO uint32_t reserved2 : 4; /* [31:28] */
} ddth12r_bit;
};
/**
* @brief dac ddth12l register, offset:0x24
*/
union
{
__IO uint32_t ddth12l;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t dd1dt12l : 12;/* [15:4] */
__IO uint32_t reserved2 : 4; /* [19:16] */
__IO uint32_t dd2dt12l : 12;/* [31:20] */
} ddth12l_bit;
};
/**
* @brief dac ddth8r register, offset:0x28
*/
union
{
__IO uint32_t ddth8r;
struct
{
__IO uint32_t dd1dt8r : 8; /* [7:0] */
__IO uint32_t dd2dt8r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ddth8r_bit;
};
/**
* @brief dac d1odt register, offset:0x2c
*/
union
{
__IO uint32_t d1odt;
struct
{
__IO uint32_t d1odt : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} d1odt_bit;
};
/**
* @brief dac d2odt register, offset:0x30
*/
union
{
__IO uint32_t d2odt;
struct
{
__IO uint32_t d2odt : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} d2odt_bit;
};
/**
* @brief dac sr register, offset:0x34
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t reserved1 : 13;/* [12:0] */
__IO uint32_t d1dmaudrf : 1; /* [13] */
__IO uint32_t reserved2 : 15;/* [28:14] */
__IO uint32_t d2dmaudrf : 1; /* [29] */
__IO uint32_t reserved3 : 2;/* [31:30] */
} sts_bit;
};
} dac_type;
/**
* @}
*/
#define DAC ((dac_type *) DAC_BASE)
/** @defgroup DAC_exported_functions
* @{
*/
void dac_reset(void);
void dac_enable(dac_select_type dac_select, confirm_state new_state);
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
void dac_software_trigger_generate(dac_select_type dac_select);
void dac_dual_software_trigger_generate(void);
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
uint16_t dac_data_output_get(dac_select_type dac_select);
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
flag_status dac_udr_flag_get(dac_select_type dac_select);
void dac_udr_flag_clear(dac_select_type dac_select);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_mcudbg.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 mcudbg header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_MCUDBG_H
#define __AT32F435_437_MCUDBG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup DEBUG
* @{
*/
/** @defgroup DEBUG_mode_definition
* @{
*/
/* debug ctrl register bit */
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
/* debug apb1 frz register bit */
#define DEBUG_TMR2_PAUSE 0x00000001 /*!< debug timer2 pause */
#define DEBUG_TMR3_PAUSE 0x00000002 /*!< debug timer3 pause */
#define DEBUG_TMR4_PAUSE 0x00000004 /*!< debug timer4 pause */
#define DEBUG_TMR5_PAUSE 0x00000008 /*!< debug timer5 pause */
#define DEBUG_TMR6_PAUSE 0x00000010 /*!< debug timer6 pause */
#define DEBUG_TMR7_PAUSE 0x00000020 /*!< debug timer7 pause */
#define DEBUG_TMR12_PAUSE 0x00000040 /*!< debug timer12 pause */
#define DEBUG_TMR13_PAUSE 0x00000080 /*!< debug timer13 pause */
#define DEBUG_TMR14_PAUSE 0x00000100 /*!< debug timer14 pause */
#define DEBUG_ERTC_PAUSE 0x00000400 /*!< debug ertc pause */
#define DEBUG_WWDT_PAUSE 0x00000800 /*!< debug window watchdog timer pause */
#define DEBUG_WDT_PAUSE 0x00001000 /*!< debug watchdog timer pause */
#define DEBUG_ERTC_512_PAUSE 0x00008000 /*!< debug ertc_512 pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x01000000 /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x08000000 /*!< debug i2c2 smbus timeout */
#define DEBUG_I2C3_SMBUS_TIMEOUT 0x10000000 /*!< debug i2c3 smbus timeout */
#define DEBUG_CAN1_PAUSE 0x02000000 /*!< debug can1 pause */
#define DEBUG_CAN2_PAUSE 0x04000000 /*!< debug can2 pause */
/* debug apb2 frz register bit */
#define DEBUG_TMR1_PAUSE 0x00000001 /*!< debug timer1 pause */
#define DEBUG_TMR8_PAUSE 0x00000002 /*!< debug timer8 pause */
#define DEBUG_TMR20_PAUSE 0x00000040 /*!< debug timer20 pause */
#define DEBUG_TMR9_PAUSE 0x00010000 /*!< debug timer9 pause */
#define DEBUG_TMR10_PAUSE 0x00020000 /*!< debug timer10 pause */
#define DEBUG_TMR11_PAUSE 0x00040000 /*!< debug timer11 pause */
/**
* @}
*/
/** @defgroup DEBUG_exported_types
* @{
*/
/**
* @brief type define debug register all
*/
typedef struct
{
/**
* @brief debug idcode register, offset:0x00
*/
union
{
__IO uint32_t pid;
struct
{
__IO uint32_t pid : 32;/* [31:0] */
} idcode_bit;
};
/**
* @brief debug ctrl register, offset:0x04
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t sleep_debug : 1;/* [0] */
__IO uint32_t deepsleep_debug : 1;/* [1] */
__IO uint32_t standby_debug : 1;/* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} ctrl_bit;
};
/**
* @brief debug apb1 frz register, offset:0x08
*/
union
{
__IO uint32_t apb1_frz;
struct
{
__IO uint32_t tmr2_pause : 1;/* [0] */
__IO uint32_t tmr3_pause : 1;/* [1] */
__IO uint32_t tmr4_pause : 1;/* [2] */
__IO uint32_t tmr5_pause : 1;/* [3] */
__IO uint32_t tmr6_pause : 1;/* [4] */
__IO uint32_t tmr7_pause : 1;/* [5] */
__IO uint32_t tmr12_pause : 1;/* [6] */
__IO uint32_t tmr13_pause : 1;/* [7] */
__IO uint32_t tmr14_pause : 1;/* [8] */
__IO uint32_t reserved1 : 1;/* [9] */
__IO uint32_t ertc_pause : 1;/* [10] */
__IO uint32_t wwdt_pause : 1;/* [11] */
__IO uint32_t wdt_pause : 1;/* [12] */
__IO uint32_t reserved2 : 2;/* [14:13] */
__IO uint32_t ertc_512_pause : 1;/* [15] */
__IO uint32_t reserved3 : 8;/* [23:16] */
__IO uint32_t i2c1_smbus_timeout : 1;/* [24] */
__IO uint32_t can1_pause : 1;/* [25] */
__IO uint32_t can2_pause : 1;/* [26] */
__IO uint32_t i2c2_smbus_timeout : 1;/* [27] */
__IO uint32_t i2c3_smbus_timeout : 1;/* [28] */
__IO uint32_t reserved4 : 3;/* [31:29] */
} apb1_frz_bit;
};
/**
* @brief debug apb2 frz register, offset:0x0c
*/
union
{
__IO uint32_t apb2_frz;
struct
{
__IO uint32_t tmr1_pause : 1;/* [0] */
__IO uint32_t tmr8_pause : 1;/* [1] */
__IO uint32_t reserved1 : 4;/* [5:2] */
__IO uint32_t tmr20_pause : 1;/* [6] */
__IO uint32_t reserved2 : 9;/* [15:7] */
__IO uint32_t tmr9_pause : 1;/* [16] */
__IO uint32_t tmr10_pause : 1;/* [17] */
__IO uint32_t tmr11_pause : 1;/* [18] */
__IO uint32_t reserved3 : 13;/* [31:19] */
} apb2_frz_bit;
};
} debug_type;
/**
* @}
*/
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
/** @defgroup DEBUG_exported_functions
* @{
*/
uint32_t debug_device_id_get(void);
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state);
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state);
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_def.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_DEF_H
#define __AT32F435_437_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* gnu compiler */
#if defined (__GNUC__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
#endif
#endif
/* arm compiler */
#if defined (__CC_ARM)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD __align(4)
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
/* iar compiler */
#if defined (__ICCARM__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
#if !defined(UNUSED)
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
#endif
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_dma.h Normal file
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@ -0,0 +1,785 @@
/**
**************************************************************************
* @file at32f435_437_dma.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dma header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_DMA_H
#define __AT32F435_437_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_interrupts_definition
* @brief dma interrupt
* @{
*/
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @brief edma flag
* @{
*/
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
/**
* @brief dmamux flag
*/
#define DMAMUX_SYNC_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux channel1 synchronization overrun event flag */
#define DMAMUX_SYNC_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux channel2 synchronization overrun event flag */
#define DMAMUX_SYNC_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux channel3 synchronization overrun event flag */
#define DMAMUX_SYNC_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux channel4 synchronization overrun event flag */
#define DMAMUX_SYNC_OV5_FLAG ((uint32_t)0x00000010) /*!< dmamux channel5 synchronization overrun event flag */
#define DMAMUX_SYNC_OV6_FLAG ((uint32_t)0x00000020) /*!< dmamux channel6 synchronization overrun event flag */
#define DMAMUX_SYNC_OV7_FLAG ((uint32_t)0x00000040) /*!< dmamux channel7 synchronization overrun event flag */
#define DMAMUX_GEN_TRIG_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux generator channel1 overrun event flag */
#define DMAMUX_GEN_TRIG_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux generator channel2 overrun event flag */
#define DMAMUX_GEN_TRIG_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux generator channel3 overrun event flag */
#define DMAMUX_GEN_TRIG_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux generator channel4 overrun event flag */
/**
* @}
*/
/** @defgroup DMA_exported_types
* @{
*/
/**
* @brief dma direction type
*/
typedef enum
{
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction: peripheral to memory */
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction: memory to peripheral */
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory */
} dma_dir_type;
/**
* @brief dma peripheral data size type
*/
typedef enum
{
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
} dma_peripheral_data_size_type;
/**
* @brief dma memory data size type
*/
typedef enum
{
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
} dma_memory_data_size_type;
/**
* @brief dma priority level type
*/
typedef enum
{
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: medium */
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
} dma_priority_level_type;
/**
* @brief dmamux request type
*/
typedef enum
{
DMAMUX_DMAREQ_ID_REQ_G1 = 0x01, /*!< dmamux channel dma request inputs resources: generator channel1 */
DMAMUX_DMAREQ_ID_REQ_G2 = 0x02, /*!< dmamux channel dma request inputs resources: generator channel2 */
DMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< dmamux channel dma request inputs resources: generator channel3 */
DMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< dmamux channel dma request inputs resources: generator channel4 */
DMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< dmamux channel dma request inputs resources: adc1 */
DMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< dmamux channel dma request inputs resources: adc2 */
DMAMUX_DMAREQ_ID_ADC3 = 0x25, /*!< dmamux channel dma request inputs resources: adc3 */
DMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< dmamux channel dma request inputs resources: dac1 */
DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< dmamux channel dma request inputs resources: timer6 overflow */
DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< dmamux channel dma request inputs resources: timer7 overflow */
DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< dmamux channel dma request inputs resources: spi1 rx */
DMAMUX_DMAREQ_ID_SPI1_TX = 0x0B, /*!< dmamux channel dma request inputs resources: spi1 tx */
DMAMUX_DMAREQ_ID_SPI2_RX = 0x0C, /*!< dmamux channel dma request inputs resources: spi2 rx */
DMAMUX_DMAREQ_ID_SPI2_TX = 0x0D, /*!< dmamux channel dma request inputs resources: spi2 tx */
DMAMUX_DMAREQ_ID_SPI3_RX = 0x0E, /*!< dmamux channel dma request inputs resources: spi3 rx */
DMAMUX_DMAREQ_ID_SPI3_TX = 0x0F, /*!< dmamux channel dma request inputs resources: spi3 tx */
DMAMUX_DMAREQ_ID_SPI4_RX = 0x6A, /*!< dmamux channel dma request inputs resources: spi4 rx */
DMAMUX_DMAREQ_ID_SPI4_TX = 0x6B, /*!< dmamux channel dma request inputs resources: spi4 tx */
DMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E, /*!< dmamux channel dma request inputs resources: i2s2_ext_rx */
DMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F, /*!< dmamux channel dma request inputs resources: i2s2_ext_tx */
DMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70, /*!< dmamux channel dma request inputs resources: i2s3_ext_rx */
DMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71, /*!< dmamux channel dma request inputs resources: i2s3_ext_tx */
DMAMUX_DMAREQ_ID_I2C1_RX = 0x10, /*!< dmamux channel dma request inputs resources: i2c1_rx */
DMAMUX_DMAREQ_ID_I2C1_TX = 0x11, /*!< dmamux channel dma request inputs resources: i2c1_tx */
DMAMUX_DMAREQ_ID_I2C2_RX = 0x12, /*!< dmamux channel dma request inputs resources: i2c2_rx */
DMAMUX_DMAREQ_ID_I2C2_TX = 0x13, /*!< dmamux channel dma request inputs resources: i2c2_tx */
DMAMUX_DMAREQ_ID_I2C3_RX = 0x14, /*!< dmamux channel dma request inputs resources: i2c3_rx */
DMAMUX_DMAREQ_ID_I2C3_TX = 0x15, /*!< dmamux channel dma request inputs resources: i2c3_tx */
DMAMUX_DMAREQ_ID_USART1_RX = 0x18, /*!< dmamux channel dma request inputs resources: usart1_rx */
DMAMUX_DMAREQ_ID_USART1_TX = 0x19, /*!< dmamux channel dma request inputs resources: usart1_tx */
DMAMUX_DMAREQ_ID_USART2_RX = 0x1A, /*!< dmamux channel dma request inputs resources: usart2_rx */
DMAMUX_DMAREQ_ID_USART2_TX = 0x1B, /*!< dmamux channel dma request inputs resources: usart2_tx */
DMAMUX_DMAREQ_ID_USART3_RX = 0x1C, /*!< dmamux channel dma request inputs resources: usart3_rx */
DMAMUX_DMAREQ_ID_USART3_TX = 0x1D, /*!< dmamux channel dma request inputs resources: usart3_tx */
DMAMUX_DMAREQ_ID_UART4_RX = 0x1E, /*!< dmamux channel dma request inputs resources: uart4_rx */
DMAMUX_DMAREQ_ID_UART4_TX = 0x1F, /*!< dmamux channel dma request inputs resources: uart4_tx */
DMAMUX_DMAREQ_ID_UART5_RX = 0x20, /*!< dmamux channel dma request inputs resources: uart5_rx */
DMAMUX_DMAREQ_ID_UART5_TX = 0x21, /*!< dmamux channel dma request inputs resources: uart5_tx */
DMAMUX_DMAREQ_ID_USART6_RX = 0x72, /*!< dmamux channel dma request inputs resources: usart6_rx */
DMAMUX_DMAREQ_ID_USART6_TX = 0x73, /*!< dmamux channel dma request inputs resources: usart6_tx */
DMAMUX_DMAREQ_ID_UART7_RX = 0x74, /*!< dmamux channel dma request inputs resources: uart7_rx */
DMAMUX_DMAREQ_ID_UART7_TX = 0x75, /*!< dmamux channel dma request inputs resources: uart7_tx */
DMAMUX_DMAREQ_ID_UART8_RX = 0x76, /*!< dmamux channel dma request inputs resources: uart8_rx */
DMAMUX_DMAREQ_ID_UART8_TX = 0x77, /*!< dmamux channel dma request inputs resources: uart8_tx */
DMAMUX_DMAREQ_ID_SDIO1 = 0x27, /*!< dmamux channel dma request inputs resources: sdio1 */
DMAMUX_DMAREQ_ID_SDIO2 = 0x67, /*!< dmamux channel dma request inputs resources: sdio2 */
DMAMUX_DMAREQ_ID_QSPI1 = 0x28, /*!< dmamux channel dma request inputs resources: qspi1 */
DMAMUX_DMAREQ_ID_QSPI2 = 0x68, /*!< dmamux channel dma request inputs resources: qspi2 */
DMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A, /*!< dmamux channel dma request inputs resources: timer1 ch1 */
DMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B, /*!< dmamux channel dma request inputs resources: timer1 ch2 */
DMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C, /*!< dmamux channel dma request inputs resources: timer1 ch3 */
DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< dmamux channel dma request inputs resources: timer1 ch4 */
DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< dmamux channel dma request inputs resources: timer1 overflow */
DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< dmamux channel dma request inputs resources: timer1 trigger */
DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
DMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31, /*!< dmamux channel dma request inputs resources: timer8 ch1 */
DMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32, /*!< dmamux channel dma request inputs resources: timer8 ch2 */
DMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33, /*!< dmamux channel dma request inputs resources: timer8 ch3 */
DMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34, /*!< dmamux channel dma request inputs resources: timer8 ch4 */
DMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35, /*!< dmamux channel dma request inputs resources: timer8 overflow */
DMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36, /*!< dmamux channel dma request inputs resources: timer8 trigger */
DMAMUX_DMAREQ_ID_TMR8_HALL = 0x37, /*!< dmamux channel dma request inputs resources: timer8 hall */
DMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38, /*!< dmamux channel dma request inputs resources: timer2 ch1 */
DMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39, /*!< dmamux channel dma request inputs resources: timer2 ch2 */
DMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A, /*!< dmamux channel dma request inputs resources: timer2 ch3 */
DMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B, /*!< dmamux channel dma request inputs resources: timer2 ch4 */
DMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C, /*!< dmamux channel dma request inputs resources: timer2 overflow */
DMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E, /*!< dmamux channel dma request inputs resources: timer2 trigger */
DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< dmamux channel dma request inputs resources: timer3 ch1 */
DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< dmamux channel dma request inputs resources: timer3 ch2 */
DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< dmamux channel dma request inputs resources: timer3 ch3 */
DMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40, /*!< dmamux channel dma request inputs resources: timer3 ch4 */
DMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41, /*!< dmamux channel dma request inputs resources: timer3 overflow */
DMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42, /*!< dmamux channel dma request inputs resources: timer3 trigger */
DMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43, /*!< dmamux channel dma request inputs resources: timer4 ch1 */
DMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44, /*!< dmamux channel dma request inputs resources: timer4 ch2 */
DMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45, /*!< dmamux channel dma request inputs resources: timer4 ch3 */
DMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46, /*!< dmamux channel dma request inputs resources: timer4 ch4 */
DMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47, /*!< dmamux channel dma request inputs resources: timer4 overflow */
DMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F, /*!< dmamux channel dma request inputs resources: timer4 trigger */
DMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48, /*!< dmamux channel dma request inputs resources: timer5 ch1 */
DMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49, /*!< dmamux channel dma request inputs resources: timer5 ch2 */
DMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A, /*!< dmamux channel dma request inputs resources: timer5 ch3 */
DMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B, /*!< dmamux channel dma request inputs resources: timer5 ch4 */
DMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C, /*!< dmamux channel dma request inputs resources: timer5 overflow */
DMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D, /*!< dmamux channel dma request inputs resources: timer5 trigger */
DMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56, /*!< dmamux channel dma request inputs resources: timer20 ch1 */
DMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57, /*!< dmamux channel dma request inputs resources: timer20 ch2 */
DMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58, /*!< dmamux channel dma request inputs resources: timer20 ch3 */
DMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59, /*!< dmamux channel dma request inputs resources: timer20 ch4 */
DMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A, /*!< dmamux channel dma request inputs resources: timer20 overflow */
DMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D, /*!< dmamux channel dma request inputs resources: timer20 trigger */
DMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E, /*!< dmamux channel dma request inputs resources: timer20 hall */
DMAMUX_DMAREQ_ID_DVP = 0x69 /*!< dmamux channel dma request inputs resources: dvp */
} dmamux_requst_id_sel_type;
/**
* @brief dmamux sync id type
*/
typedef enum
{
DMAMUX_SYNC_ID_EXINT0 = 0x00, /*!< dmamux channel synchronization inputs resources: exint line0 */
DMAMUX_SYNC_ID_EXINT1 = 0x01, /*!< dmamux channel synchronization inputs resources: exint line1 */
DMAMUX_SYNC_ID_EXINT2 = 0x02, /*!< dmamux channel synchronization inputs resources: exint line2 */
DMAMUX_SYNC_ID_EXINT3 = 0x03, /*!< dmamux channel synchronization inputs resources: exint line3 */
DMAMUX_SYNC_ID_EXINT4 = 0x04, /*!< dmamux channel synchronization inputs resources: exint line4 */
DMAMUX_SYNC_ID_EXINT5 = 0x05, /*!< dmamux channel synchronization inputs resources: exint line5 */
DMAMUX_SYNC_ID_EXINT6 = 0x06, /*!< dmamux channel synchronization inputs resources: exint line6 */
DMAMUX_SYNC_ID_EXINT7 = 0x07, /*!< dmamux channel synchronization inputs resources: exint line7 */
DMAMUX_SYNC_ID_EXINT8 = 0x08, /*!< dmamux channel synchronization inputs resources: exint line8 */
DMAMUX_SYNC_ID_EXINT9 = 0x09, /*!< dmamux channel synchronization inputs resources: exint line9 */
DMAMUX_SYNC_ID_EXINT10 = 0x0A, /*!< dmamux channel synchronization inputs resources: exint line10 */
DMAMUX_SYNC_ID_EXINT11 = 0x0B, /*!< dmamux channel synchronization inputs resources: exint line11 */
DMAMUX_SYNC_ID_EXINT12 = 0x0C, /*!< dmamux channel synchronization inputs resources: exint line12 */
DMAMUX_SYNC_ID_EXINT13 = 0x0D, /*!< dmamux channel synchronization inputs resources: exint line13 */
DMAMUX_SYNC_ID_EXINT14 = 0x0E, /*!< dmamux channel synchronization inputs resources: exint line14 */
DMAMUX_SYNC_ID_EXINT15 = 0x0F, /*!< dmamux channel synchronization inputs resources: exint line15 */
DMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux channel synchronization inputs resources: dmamux channel1 event */
DMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux channel synchronization inputs resources: dmamux channel2 event */
DMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux channel synchronization inputs resources: dmamux channel3 event */
DMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux channel synchronization inputs resources: dmamux channel4 event */
DMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux channel synchronization inputs resources: dmamux channel5 event */
DMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux channel synchronization inputs resources: dmamux channel6 event */
DMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux channel synchronization inputs resources: dmamux channel7 event */
} dmamux_sync_id_sel_type;
/**
* @brief dmamux sync polarity type
*/
typedef enum
{
DMAMUX_SYNC_POLARITY_DISABLE = 0x00, /*!< dmamux channel synchronization inputs resources polarity default value */
DMAMUX_SYNC_POLARITY_RISING = 0x01, /*!< dmamux channel synchronization inputs resources polarity: rising */
DMAMUX_SYNC_POLARITY_FALLING = 0x02, /*!< dmamux channel synchronization inputs resources polarity: falling */
DMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03 /*!< dmamux channel synchronization inputs resources polarity: rising_falling */
} dmamux_sync_pol_type;
/**
* @brief dmamux generator id type
*/
typedef enum
{
DMAMUX_GEN_ID_EXINT0 = 0x00, /*!< dmamux generator channel inputs resources: exint line0 */
DMAMUX_GEN_ID_EXINT1 = 0x01, /*!< dmamux generator channel inputs resources: exint line1 */
DMAMUX_GEN_ID_EXINT2 = 0x02, /*!< dmamux generator channel inputs resources: exint line2 */
DMAMUX_GEN_ID_EXINT3 = 0x03, /*!< dmamux generator channel inputs resources: exint line3 */
DMAMUX_GEN_ID_EXINT4 = 0x04, /*!< dmamux generator channel inputs resources: exint line4 */
DMAMUX_GEN_ID_EXINT5 = 0x05, /*!< dmamux generator channel inputs resources: exint line5 */
DMAMUX_GEN_ID_EXINT6 = 0x06, /*!< dmamux generator channel inputs resources: exint line6 */
DMAMUX_GEN_ID_EXINT7 = 0x07, /*!< dmamux generator channel inputs resources: exint line7 */
DMAMUX_GEN_ID_EXINT8 = 0x08, /*!< dmamux generator channel inputs resources: exint line8 */
DMAMUX_GEN_ID_EXINT9 = 0x09, /*!< dmamux generator channel inputs resources: exint line9 */
DMAMUX_GEN_ID_EXINT10 = 0x0A, /*!< dmamux generator channel inputs resources: exint line10 */
DMAMUX_GEN_ID_EXINT11 = 0x0B, /*!< dmamux generator channel inputs resources: exint line11 */
DMAMUX_GEN_ID_EXINT12 = 0x0C, /*!< dmamux generator channel inputs resources: exint line12 */
DMAMUX_GEN_ID_EXINT13 = 0x0D, /*!< dmamux generator channel inputs resources: exint line13 */
DMAMUX_GEN_ID_EXINT14 = 0x0E, /*!< dmamux generator channel inputs resources: exint line14 */
DMAMUX_GEN_ID_EXINT15 = 0x0F, /*!< dmamux generator channel inputs resources: exint line15 */
DMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux generator channel inputs resources: dmamux channel1 event */
DMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux generator channel inputs resources: dmamux channel2 event */
DMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux generator channel inputs resources: dmamux channel3 event */
DMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux generator channel inputs resources: dmamux channel4 event */
DMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux generator channel inputs resources: dmamux channel5 event */
DMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux generator channel inputs resources: dmamux channel6 event */
DMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux generator channel inputs resources: dmamux channel7 event */
} dmamux_gen_id_sel_type;
/**
* @brief dmamux generator polarity type
*/
typedef enum
{
DMAMUX_GEN_POLARITY_DISABLE = 0x00, /*!< dmamux generator channel inputs resources polarity default value */
DMAMUX_GEN_POLARITY_RISING = 0x01, /*!< dmamux generator channel inputs resources polarity: rising */
DMAMUX_GEN_POLARITY_FALLING = 0x02, /*!< dmamux generator channel inputs resources polarity: falling */
DMAMUX_GEN_POLARITY_RISING_FALLING = 0x03 /*!< dmamux generator channel inputs resources polarity: rising_falling */
} dmamux_gen_pol_type;
/**
* @brief dma init type
*/
typedef struct
{
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
uint32_t memory_base_addr; /*!< base addrress for memory */
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
uint16_t buffer_size; /*!< counter to transfer (0~0xFFFF) */
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
confirm_state loop_mode_enable; /*!< when loop mode enable, buffer size will reload if count to 0*/
dma_priority_level_type priority; /*!< dma priority can choose from very high,high,dedium or low */
} dma_init_type;
/**
* @brief dmamux sync init type
*/
typedef struct
{
dmamux_sync_id_sel_type sync_signal_sel; /*!< dma dmamux synchronization input select */
uint32_t sync_polarity; /*!< dma dmamux synchronization polarity */
uint32_t sync_request_number; /*!< dma dmamux number of dma requests before an output event is generated */
confirm_state sync_event_enable; /*!< dma dmamux event generation disabled */
confirm_state sync_enable; /*!< dma dmamux synchronization enable */
} dmamux_sync_init_type;
/**
* @brief dmamux generator init type
*/
typedef struct
{
dmamux_gen_id_sel_type gen_signal_sel; /*!< dma dmamux generator dma request trigger input select */
dmamux_gen_pol_type gen_polarity; /*!< dma dmamux generator trigger polarity */
uint32_t gen_request_number; /*!< dma dmamux the number of dma requests to be generated after a trigger event */
confirm_state gen_enable; /*!< dma dmamux generator enable */
} dmamux_gen_init_type;
/**
* @brief type define dma1 register
*/
typedef struct
{
/**
* @brief dma sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t gf1 : 1; /* [0] */
__IO uint32_t fdtf1 : 1; /* [1] */
__IO uint32_t hdtf1 : 1; /* [2] */
__IO uint32_t dterrf1 : 1; /* [3] */
__IO uint32_t gf2 : 1; /* [4] */
__IO uint32_t fdtf2 : 1; /* [5] */
__IO uint32_t hdtf2 : 1; /* [6] */
__IO uint32_t dterrf2 : 1; /* [7] */
__IO uint32_t gf3 : 1; /* [8] */
__IO uint32_t fdtf3 : 1; /* [9] */
__IO uint32_t hdtf3 : 1; /* [10] */
__IO uint32_t dterrf3 : 1; /* [11] */
__IO uint32_t gf4 : 1; /* [12] */
__IO uint32_t fdtf4 : 1; /* [13] */
__IO uint32_t hdtf4 : 1; /* [14] */
__IO uint32_t dterrf4 : 1; /* [15] */
__IO uint32_t gf5 : 1; /* [16] */
__IO uint32_t fdtf5 : 1; /* [17] */
__IO uint32_t hdtf5 : 1; /* [18] */
__IO uint32_t dterrf5 : 1; /* [19] */
__IO uint32_t gf6 : 1; /* [20] */
__IO uint32_t fdtf6 : 1; /* [21] */
__IO uint32_t hdtf6 : 1; /* [22] */
__IO uint32_t dterrf6 : 1; /* [23] */
__IO uint32_t gf7 : 1; /* [24] */
__IO uint32_t fdtf7 : 1; /* [25] */
__IO uint32_t hdtf7 : 1; /* [26] */
__IO uint32_t dterrf7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} sts_bit;
};
/**
* @brief dma clr register, offset:0x04
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t gfc1 : 1; /* [0] */
__IO uint32_t fdtfc1 : 1; /* [1] */
__IO uint32_t hdtfc1 : 1; /* [2] */
__IO uint32_t dterrfc1 : 1; /* [3] */
__IO uint32_t gfc2 : 1; /* [4] */
__IO uint32_t fdtfc2 : 1; /* [5] */
__IO uint32_t hdtfc2 : 1; /* [6] */
__IO uint32_t dterrfc2 : 1; /* [7] */
__IO uint32_t gfc3 : 1; /* [8] */
__IO uint32_t fdtfc3 : 1; /* [9] */
__IO uint32_t hdtfc3 : 1; /* [10] */
__IO uint32_t dterrfc3 : 1; /* [11] */
__IO uint32_t gfc4 : 1; /* [12] */
__IO uint32_t fdtfc4 : 1; /* [13] */
__IO uint32_t hdtfc4 : 1; /* [14] */
__IO uint32_t dterrfc4 : 1; /* [15] */
__IO uint32_t gfc5 : 1; /* [16] */
__IO uint32_t fdtfc5 : 1; /* [17] */
__IO uint32_t hdtfc5 : 1; /* [18] */
__IO uint32_t dterrfc5 : 1; /* [19] */
__IO uint32_t gfc6 : 1; /* [20] */
__IO uint32_t fdtfc6 : 1; /* [21] */
__IO uint32_t hdtfc6 : 1; /* [22] */
__IO uint32_t dterrfc6 : 1; /* [23] */
__IO uint32_t gfc7 : 1; /* [24] */
__IO uint32_t fdtfc7 : 1; /* [25] */
__IO uint32_t hdtfc7 : 1; /* [26] */
__IO uint32_t dterrfc7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} clr_bit;
};
/**
* @brief reserved, offset:0x08~0xFC
*/
__IO uint32_t reserved1[62];
/**
* @brief dmamux sel register, offset:0x100
*/
union
{
__IO uint32_t muxsel;
struct
{
__IO uint32_t tblsel : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
}muxsel_bit;
};
/**
* @brief reserved, offset:0x104~0x12C
*/
__IO uint32_t reserved2[11];
/**
* @brief dmamux syncsts register, offset:0x130
*/
union
{
__IO uint32_t muxsyncsts;
struct
{
__IO uint32_t syncovf : 7; /* [6:0] */
__IO uint32_t reserved1 : 25;/* [31:7] */
}muxsyncsts_bit;
};
/**
* @brief dmamux syncclr register, offset:0x134
*/
union
{
__IO uint32_t muxsyncclr;
struct
{
__IO uint32_t syncovfc : 7; /* [6:0] */
__IO uint32_t reserved1 : 25;/* [31:7] */
}muxsyncclr_bit;
};
/**
* @brief dmamux request generator status register, offset:0x138
*/
union
{
__IO uint32_t muxgsts;
struct
{
__IO uint32_t trgovf : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:4] */
}muxgsts_bit;
};
/**
* @brief dmamux request generator status clear register, offset:0x13C
*/
union
{
__IO uint32_t muxgclr;
struct
{
__IO uint32_t trgovfc : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:4] */
}muxgclr_bit;
};
} dma_type;
/**
* @brief type define dma channel register all
*/
typedef struct
{
/**
* @brief dma ch ctrl0 register, offset:0x08+20*(x-1) x=1...7
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t chen : 1; /* [0] */
__IO uint32_t fdtien : 1; /* [1] */
__IO uint32_t hdtien : 1; /* [2] */
__IO uint32_t dterrien : 1; /* [3] */
__IO uint32_t dtd : 1; /* [4] */
__IO uint32_t lm : 1; /* [5] */
__IO uint32_t pincm : 1; /* [6] */
__IO uint32_t mincm : 1; /* [7] */
__IO uint32_t pwidth : 2; /* [9:8] */
__IO uint32_t mwidth : 2; /* [11:10] */
__IO uint32_t chpl : 2; /* [13:12] */
__IO uint32_t m2m : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} ctrl_bit;
};
/**
* @brief dma tcnt register, offset:0x0C+20*(x-1) x=1...7
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dtcnt_bit;
};
/**
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
*/
union
{
__IO uint32_t paddr;
struct
{
__IO uint32_t paddr : 32;/* [31:0] */
} paddr_bit;
};
/**
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
*/
union
{
__IO uint32_t maddr;
struct
{
__IO uint32_t maddr : 32;/* [31:0] */
} maddr_bit;
};
} dma_channel_type;
/**
* @brief type define dmamux muxsctrl register
*/
typedef struct
{
/**
* @brief dma muxsctrl register
*/
union
{
__IO uint32_t muxctrl;
struct
{
__IO uint32_t reqsel : 7; /* [6:0] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t syncovien : 1; /* [8] */
__IO uint32_t evtgen : 1; /* [9] */
__IO uint32_t reserved2 : 6; /* [15:10] */
__IO uint32_t syncen : 1; /* [16] */
__IO uint32_t syncpol : 2; /* [18:17] */
__IO uint32_t reqcnt : 5; /* [23:19] */
__IO uint32_t syncsel : 5; /* [28:24] */
__IO uint32_t reserved3 : 3; /* [31:29] */
}muxctrl_bit;
};
} dmamux_channel_type;
/**
* @brief type define dmamux request generator register all
*/
typedef struct
{
/**
* @brief dmamux request generator register, offset:0x120+4*(x-1) x=1...4
*/
union
{
__IO uint32_t gctrl;
struct
{
__IO uint32_t sigsel : 5; /* [4:0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t trgovien : 1; /* [8] */
__IO uint32_t reserved2 : 7; /* [15:9] */
__IO uint32_t gen : 1; /* [16] */
__IO uint32_t gpol : 2; /* [18:17] */
__IO uint32_t greqcnt : 5; /* [23:19] */
__IO uint32_t reserved3 : 8; /* [31:24] */
}gctrl_bit;
};
} dmamux_generator_type;
/**
* @}
*/
#define DMA1 ((dma_type *) DMA1_BASE)
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
#define DMA1MUX_CHANNEL1 ((dmamux_channel_type *) DMA1MUX_CHANNEL1_BASE)
#define DMA1MUX_CHANNEL2 ((dmamux_channel_type *) DMA1MUX_CHANNEL2_BASE)
#define DMA1MUX_CHANNEL3 ((dmamux_channel_type *) DMA1MUX_CHANNEL3_BASE)
#define DMA1MUX_CHANNEL4 ((dmamux_channel_type *) DMA1MUX_CHANNEL4_BASE)
#define DMA1MUX_CHANNEL5 ((dmamux_channel_type *) DMA1MUX_CHANNEL5_BASE)
#define DMA1MUX_CHANNEL6 ((dmamux_channel_type *) DMA1MUX_CHANNEL6_BASE)
#define DMA1MUX_CHANNEL7 ((dmamux_channel_type *) DMA1MUX_CHANNEL7_BASE)
#define DMA1MUX_GENERATOR1 ((dmamux_generator_type *) DMA1MUX_GENERATOR1_BASE)
#define DMA1MUX_GENERATOR2 ((dmamux_generator_type *) DMA1MUX_GENERATOR2_BASE)
#define DMA1MUX_GENERATOR3 ((dmamux_generator_type *) DMA1MUX_GENERATOR3_BASE)
#define DMA1MUX_GENERATOR4 ((dmamux_generator_type *) DMA1MUX_GENERATOR4_BASE)
#define DMA2 ((dma_type *) DMA2_BASE)
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
#define DMA2MUX_CHANNEL1 ((dmamux_channel_type *) DMA2MUX_CHANNEL1_BASE)
#define DMA2MUX_CHANNEL2 ((dmamux_channel_type *) DMA2MUX_CHANNEL2_BASE)
#define DMA2MUX_CHANNEL3 ((dmamux_channel_type *) DMA2MUX_CHANNEL3_BASE)
#define DMA2MUX_CHANNEL4 ((dmamux_channel_type *) DMA2MUX_CHANNEL4_BASE)
#define DMA2MUX_CHANNEL5 ((dmamux_channel_type *) DMA2MUX_CHANNEL5_BASE)
#define DMA2MUX_CHANNEL6 ((dmamux_channel_type *) DMA2MUX_CHANNEL6_BASE)
#define DMA2MUX_CHANNEL7 ((dmamux_channel_type *) DMA2MUX_CHANNEL7_BASE)
#define DMA2MUX_GENERATOR1 ((dmamux_generator_type *) DMA2MUX_GENERATOR1_BASE)
#define DMA2MUX_GENERATOR2 ((dmamux_generator_type *) DMA2MUX_GENERATOR2_BASE)
#define DMA2MUX_GENERATOR3 ((dmamux_generator_type *) DMA2MUX_GENERATOR3_BASE)
#define DMA2MUX_GENERATOR4 ((dmamux_generator_type *) DMA2MUX_GENERATOR4_BASE)
/** @defgroup DMA_exported_functions
* @{
*/
/* dma controller function */
void dma_reset(dma_channel_type *dmax_channely);
void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type *dma_init_struct);
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
/* dma requst multiplexer function */
void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
void dmamux_enable(dma_type *dma_x, confirm_state new_state);
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct);
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct);
void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct);
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct);
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_dvp.h Normal file
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@ -0,0 +1,622 @@
/**
**************************************************************************
* @file at32f435_437_dvp.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dvp header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_DVP_H
#define __AT32F435_437_DVP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup DVP
* @{
*/
/** @defgroup DVP_event_flags_definition
* @brief dvp event flag
* @{
*/
#define DVP_CFD_EVT_FLAG ((uint32_t)0x00000001) /*!< capture frame done event status flag */
#define DVP_OVR_EVT_FLAG ((uint32_t)0x00000002) /*!< data fifo overrun event status flag */
#define DVP_ESE_EVT_FLAG ((uint32_t)0x00000004) /*!< embedded synchronization error event status flag */
#define DVP_VS_EVT_FLAG ((uint32_t)0x00000008) /*!< vertical synchonization event status flag */
#define DVP_HS_EVT_FLAG ((uint32_t)0x00000010) /*!< horizontal synchonization event status flag */
/**
* @}
*/
/** @defgroup DVP_interrupt_flags_definition
* @brief dvp interrupt flag
* @{
*/
#define DVP_CFD_INT_FLAG ((uint32_t)0x80000001) /*!< capture frame done interrupt status flag */
#define DVP_OVR_INT_FLAG ((uint32_t)0x80000002) /*!< data fifo overrun interrupt status flag */
#define DVP_ESE_INT_FLAG ((uint32_t)0x80000004) /*!< embedded synchronization error interrupt status flag */
#define DVP_VS_INT_FLAG ((uint32_t)0x80000008) /*!< vertical synchonization interrupt status flag */
#define DVP_HS_INT_FLAG ((uint32_t)0x80000010) /*!< horizontal synchonization interrupt status flag */
/**
* @}
*/
/** @defgroup DVP_interrupts_definition
* @brief dvp interrupt
* @{
*/
#define DVP_CFD_INT ((uint32_t)0x00000001) /*!< capture frame done interrupt */
#define DVP_OVR_INT ((uint32_t)0x00000002) /*!< data fifo overrun interrupt */
#define DVP_ESE_INT ((uint32_t)0x00000004) /*!< embedded synchronization error interrupt */
#define DVP_VS_INT ((uint32_t)0x00000008) /*!< vertical synchonization interrupt */
#define DVP_HS_INT ((uint32_t)0x00000010) /*!< horizontal synchonization interrupt */
/**
* @}
*/
/** @defgroup DVP_exported_types
* @{
*/
/**
* @brief dvp cfm type
*/
typedef enum
{
DVP_CAP_FUNC_MODE_CONTINUOUS = 0x00,
DVP_CAP_FUNC_MODE_SINGLE = 0x01
} dvp_cfm_type;
/**
* @brief dvp sm type
*/
typedef enum
{
DVP_SYNC_MODE_HARDWARE = 0x00,
DVP_SYNC_MODE_EMBEDDED = 0x01
} dvp_sm_type;
/**
* @brief dvp ckp type
*/
typedef enum
{
DVP_CLK_POLARITY_RISING = 0x00,
DVP_CLK_POLARITY_FALLING = 0x01
} dvp_ckp_type;
/**
* @brief dvp hsp type
*/
typedef enum
{
DVP_HSYNC_POLARITY_HIGH = 0x00,
DVP_HSYNC_POLARITY_LOW = 0x01
} dvp_hsp_type;
/**
* @brief dvp vsp type
*/
typedef enum
{
DVP_VSYNC_POLARITY_LOW = 0x00,
DVP_VSYNC_POLARITY_HIGH = 0x01
} dvp_vsp_type;
/**
* @brief dvp bfrc type
*/
typedef enum
{
DVP_BFRC_ALL = 0x00,
DVP_BFRC_HALF = 0x01,
DVP_BFRC_QUARTER = 0x02
} dvp_bfrc_type;
/**
* @brief dvp pdl type
*/
typedef enum
{
DVP_PIXEL_DATA_LENGTH_8 = 0x00,
DVP_PIXEL_DATA_LENGTH_10 = 0x01,
DVP_PIXEL_DATA_LENGTH_12 = 0x02,
DVP_PIXEL_DATA_LENGTH_14 = 0x03
} dvp_pdl_type;
/**
* @brief dvp pcdc type
*/
typedef enum
{
DVP_PCDC_ALL = 0x00,
DVP_PCDC_ONE_IN_TWO = 0x01,
DVP_PCDC_ONE_IN_FOUR = 0x02,
DVP_PCDC_TWO_IN_FOUR = 0x03
} dvp_pcdc_type;
/**
* @brief dvp pcds type
*/
typedef enum
{
DVP_PCDS_CAP_FIRST = 0x00,
DVP_PCDS_DROP_FIRST = 0x01
} dvp_pcds_type;
/**
* @brief dvp lcdc type
*/
typedef enum
{
DVP_LCDC_ALL = 0x00,
DVP_LCDC_ONE_IN_TWO = 0x01
} dvp_lcdc_type;
/**
* @brief dvp lcds type
*/
typedef enum
{
DVP_LCDS_CAP_FIRST = 0x00,
DVP_LCDS_DROP_FIRST = 0x01
} dvp_lcds_type;
/**
* @brief dvp status basic type
*/
typedef enum
{
DVP_STATUS_HSYN = 0x00,
DVP_STATUS_VSYN = 0x01,
DVP_STATUS_OFNE = 0x02
} dvp_status_basic_type;
/**
* @brief dvp pcdes type
*/
typedef enum
{
DVP_PCDES_CAP_FIRST = 0x00,
DVP_PCDES_DROP_FIRST = 0x01
} dvp_pcdes_type;
/**
* @brief dvp efdf type
*/
typedef enum
{
DVP_EFDF_BYPASS = 0x00,
DVP_EFDF_YUV422_UYVY = 0x04,
DVP_EFDF_YUV422_YUYV = 0x05,
DVP_EFDF_RGB565_555 = 0x06,
DVP_EFDF_Y8 = 0x07
} dvp_efdf_type;
/**
* @brief dvp idus type
*/
typedef enum
{
DVP_IDUS_MSB = 0x00,
DVP_IDUS_LSB = 0x01
} dvp_idus_type;
/**
* @brief dvp dmabt type
*/
typedef enum
{
DVP_DMABT_SINGLE = 0x00,
DVP_DMABT_BURST = 0x01
} dvp_dmabt_type;
/**
* @brief dvp hseid type
*/
typedef enum
{
DVP_HSEID_LINE_END = 0x00,
DVP_HSEID_LINE_START = 0x01
} dvp_hseid_type;
/**
* @brief dvp vseid type
*/
typedef enum
{
DVP_VSEID_FRAME_END = 0x00,
DVP_VSEID_FRMAE_START = 0x01
} dvp_vseid_type;
/**
* @brief dvp idun type
*/
typedef enum
{
DVP_IDUN_0 = 0x00,
DVP_IDUN_2 = 0x01,
DVP_IDUN_4 = 0x02,
DVP_IDUN_6 = 0x03
} dvp_idun_type;
typedef struct
{
/**
* @brief dvp ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t cap : 1; /* [0] */
__IO uint32_t cfm : 1; /* [1] */
__IO uint32_t crp : 1; /* [2] */
__IO uint32_t jpeg : 1; /* [3] */
__IO uint32_t sm : 1; /* [4] */
__IO uint32_t ckp : 1; /* [5] */
__IO uint32_t hsp : 1; /* [6] */
__IO uint32_t vsp : 1; /* [7] */
__IO uint32_t bfrc : 2; /* [9:8] */
__IO uint32_t pdl : 2; /* [11:10] */
__IO uint32_t reserved1 : 2; /* [13:12] */
__IO uint32_t ena : 1; /* [14] */
__IO uint32_t reserved2 : 1; /* [15] */
__IO uint32_t pcdc : 2; /* [17:16] */
__IO uint32_t pcds : 1; /* [18] */
__IO uint32_t lcdc : 1; /* [19] */
__IO uint32_t lcds : 1; /* [20] */
__IO uint32_t : 11;/* [31:21] */
} ctrl_bit;
};
/**
* @brief dvp sts register, offset:0x04
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t hsyn : 1; /* [0] */
__IO uint32_t vsyn : 1; /* [1] */
__IO uint32_t ofne : 1; /* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} sts_bit;
};
/**
* @brief dvp ests register, offset:0x08
*/
union
{
__IO uint32_t ests;
struct
{
__IO uint32_t cfdes : 1; /* [0] */
__IO uint32_t ovres : 1; /* [1] */
__IO uint32_t esees : 1; /* [2] */
__IO uint32_t vses : 1; /* [3] */
__IO uint32_t hses : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} ests_bit;
};
/**
* @brief dvp ier register, offset:0x0C
*/
union
{
__IO uint32_t ier;
struct
{
__IO uint32_t cfdie : 1; /* [0] */
__IO uint32_t ovrie : 1; /* [1] */
__IO uint32_t eseie : 1; /* [2] */
__IO uint32_t vsie : 1; /* [3] */
__IO uint32_t hsie : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} ier_bit;
};
/**
* @brief dvp ists register, offset:0x10
*/
union
{
__IO uint32_t ists;
struct
{
__IO uint32_t cfdis : 1; /* [0] */
__IO uint32_t ovris : 1; /* [1] */
__IO uint32_t eseis : 1; /* [2] */
__IO uint32_t vsis : 1; /* [3] */
__IO uint32_t hsis : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} ists_bit;
};
/**
* @brief dvp iclr register, offset:0x14
*/
union
{
__IO uint32_t iclr;
struct
{
__IO uint32_t cfdic : 1; /* [0] */
__IO uint32_t ovric : 1; /* [1] */
__IO uint32_t eseic : 1; /* [2] */
__IO uint32_t vsic : 1; /* [3] */
__IO uint32_t hsic : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} iclr_bit;
};
/**
* @brief dvp scr register, offset:0x18
*/
union
{
__IO uint32_t scr;
struct
{
__IO uint32_t fmsc : 8; /* [7:0] */
__IO uint32_t lnsc : 8; /* [15:8] */
__IO uint32_t lnec : 8; /* [23:16] */
__IO uint32_t fmec : 8; /* [31:24] */
} scr_bit;
};
/**
* @brief dvp sur register, offset:0x1C
*/
union
{
__IO uint32_t sur;
struct
{
__IO uint32_t fmsu : 8; /* [7:0] */
__IO uint32_t lnsu : 8; /* [15:8] */
__IO uint32_t lneu : 8; /* [23:16] */
__IO uint32_t fmeu : 8; /* [31:24] */
} sur_bit;
};
/**
* @brief dvp cwst register, offset:0x20
*/
union
{
__IO uint32_t cwst;
struct
{
__IO uint32_t chstr : 14;/* [13:0] */
__IO uint32_t reserved1 : 2; /* [15:14] */
__IO uint32_t cvstr : 13;/* [28:16] */
__IO uint32_t reserved2 : 3; /* [31:29] */
} cwst_bit;
};
/**
* @brief dvp cwsz register, offset:0x24
*/
union
{
__IO uint32_t cwsz;
struct
{
__IO uint32_t chnum : 14;/* [13:0] */
__IO uint32_t reserved1 : 2; /* [15:14] */
__IO uint32_t cvnum : 14;/* [29:16] */
__IO uint32_t reserved2 : 2; /* [31:30] */
} cwsz_bit;
};
/**
* @brief dvp dt register, offset:0x28
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dr0 : 8; /* [7:0] */
__IO uint32_t dr1 : 8; /* [15:8] */
__IO uint32_t dr2 : 8; /* [23:16] */
__IO uint32_t dr3 : 8; /* [31:24] */
} dt_bit;
};
/**
* @brief dvp reserved1 register, offset:0x2C-0x3C
*/
__IO uint32_t reserved1[5];
/**
* @brief dvp actrl register, offset:0x40
*/
union
{
__IO uint32_t actrl;
struct
{
__IO uint32_t eisre : 1; /* [0] */
__IO uint32_t efrce : 1; /* [1] */
__IO uint32_t mibe : 1; /* [2] */
__IO uint32_t pcdes : 1; /* [3] */
__IO uint32_t efdf : 3; /* [6:4] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t idun : 2; /* [9:8] */
__IO uint32_t idus : 1; /* [10] */
__IO uint32_t reserved2 : 1; /* [11] */
__IO uint32_t dmabt : 1; /* [12] */
__IO uint32_t reserved3 : 1; /* [13] */
__IO uint32_t reserved4 : 1; /* [14] */
__IO uint32_t reserved5 : 1; /* [15] */
__IO uint32_t hseid : 1; /* [16] */
__IO uint32_t vseid : 1; /* [17] */
__IO uint32_t reserved6 : 1; /* [18] */
__IO uint32_t reserved7 : 2; /* [20:19] */
__IO uint32_t reserved8 : 11;/* [31:21] */
} actrl_bit;
};
/**
* @brief dvp reserved2 register, offset:0x44
*/
__IO uint32_t reserved2;
/**
* @brief dvp hscf register, offset:0x48
*/
union
{
__IO uint32_t hscf;
struct
{
__IO uint32_t hsrss : 13;/* [12:0] */
__IO uint32_t reserved1 : 3; /* [15:13] */
__IO uint32_t hsrts : 13;/* [28:16] */
__IO uint32_t reserved2 : 3; /* [31:29] */
} hscf_bit;
};
/**
* @brief dvp vscf register, offset:0x4C
*/
union
{
__IO uint32_t vscf;
struct
{
__IO uint32_t vsrss : 13;/* [12:0] */
__IO uint32_t reserved1 : 3; /* [15:13] */
__IO uint32_t vsrts : 13;/* [28:16] */
__IO uint32_t reserved2 : 3; /* [31:29] */
} vscf_bit;
};
/**
* @brief dvp frf register, offset:0x50
*/
union
{
__IO uint32_t frf;
struct
{
__IO uint32_t efrcsf : 5; /* [4:0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t efrctf : 5; /* [12:8] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} frf_bit;
};
/**
* @brief dvp bth register, offset:0x54
*/
union
{
__IO uint32_t bth;
struct
{
__IO uint32_t mibthd : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} bth_bit;
};
} dvp_type;
/**
* @}
*/
#define DVP ((dvp_type *) DVP_BASE)
/** @defgroup DVP_exported_functions
* @{
*/
void dvp_reset(void);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_mode_set(dvp_cfm_type cap_mode);
void dvp_window_crop_enable(confirm_state new_state);
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes);
void dvp_jpeg_enable(confirm_state new_state);
void dvp_sync_mode_set(dvp_sm_type sync_mode);
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu);
void dvp_pclk_polarity_set(dvp_ckp_type eage);
void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol);
void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
void dvp_enable(confirm_state new_state);
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes);
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
flag_status dvp_flag_get(uint32_t flag);
void dvp_flag_clear(uint32_t flag);
void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state);
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun);
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_exint.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 exint header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_EXINT_H
#define __AT32F435_437_EXINT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup EXINT
* @{
*/
/** @defgroup EXINT_lines
* @{
*/
#define EXINT_LINE_NONE ((uint32_t)0x000000)
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 */
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 */
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 */
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
#define EXINT_LINE_20 ((uint32_t)0x100000) /*!< external interrupt line 20 */
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 */
#define EXINT_LINE_22 ((uint32_t)0x400000) /*!< external interrupt line 22 */
/**
* @}
*/
/** @defgroup EXINT_exported_types
* @{
*/
/**
* @brief exint line mode type
*/
typedef enum
{
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
} exint_line_mode_type;
/**
* @brief exint polarity configuration type
*/
typedef enum
{
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
} exint_polarity_config_type;
/**
* @brief exint init type
*/
typedef struct
{
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
confirm_state line_enable; /*!< enable or disable exint */
} exint_init_type;
/**
* @brief type define exint register all
*/
typedef struct
{
/**
* @brief exint inten register, offset:0x00
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t intenx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} inten_bit;
};
/**
* @brief exint evten register, offset:0x04
*/
union
{
__IO uint32_t evten;
struct
{
__IO uint32_t evtenx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} evten_bit;
};
/**
* @brief exint polcfg1 register, offset:0x08
*/
union
{
__IO uint32_t polcfg1;
struct
{
__IO uint32_t rpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} polcfg1_bit;
};
/**
* @brief exint polcfg2 register, offset:0x0C
*/
union
{
__IO uint32_t polcfg2;
struct
{
__IO uint32_t fpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} polcfg2_bit;
};
/**
* @brief exint swtrg register, offset:0x10
*/
union
{
__IO uint32_t swtrg;
struct
{
__IO uint32_t swtx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} swtrg_bit;
};
/**
* @brief exint intsts register, offset:0x14
*/
union
{
__IO uint32_t intsts;
struct
{
__IO uint32_t linex : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} intsts_bit;
};
} exint_type;
/**
* @}
*/
#define EXINT ((exint_type *) EXINT_BASE)
/** @defgroup EXINT_exported_functions
* @{
*/
void exint_reset(void);
void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_flash.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 flash header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_FLASH_H
#define __AT32F435_437_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_exported_constants
* @{
*/
/**
* @brief flash unlock keys
*/
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
/**
* @brief flash bank address
*/
#if defined (AT32F435CMU7) || defined (AT32F435CMT7) || defined (AT32F435RMT7) || \
defined (AT32F435VMT7) || defined (AT32F435ZMT7) || defined (AT32F437RMT7) || \
defined (AT32F437VMT7) || defined (AT32F437ZMT7)
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
#define FLASH_BANK1_END_ADDR ((uint32_t)0x081FFFFF) /*!< flash end address of bank1 */
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08200000) /*!< flash start address of bank2 */
#define FLASH_BANK2_END_ADDR ((uint32_t)0x083EFFFF) /*!< flash end address of bank2 */
#else
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
#define FLASH_BANK1_END_ADDR ((uint32_t)0x0807FFFF) /*!< flash end address of bank1 */
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08080000) /*!< flash start address of bank2 */
#define FLASH_BANK2_END_ADDR ((uint32_t)0x080FFFFF) /*!< flash end address of bank2 */
#endif
/**
* @brief flash flag
*/
#define FLASH_OBF_FLAG FLASH_BANK1_OBF_FLAG /*!< flash operate busy flag */
#define FLASH_ODF_FLAG FLASH_BANK1_ODF_FLAG /*!< flash operate done flag */
#define FLASH_PRGMERR_FLAG FLASH_BANK1_PRGMERR_FLAG /*!< flash program error flag */
#define FLASH_EPPERR_FLAG FLASH_BANK1_EPPERR_FLAG /*!< flash erase/program protection error flag */
#define FLASH_BANK1_OBF_FLAG ((uint32_t)0x00000001) /*!< flash bank1 operate busy flag */
#define FLASH_BANK1_ODF_FLAG ((uint32_t)0x00000020) /*!< flash bank1 operate done flag */
#define FLASH_BANK1_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash bank1 program error flag */
#define FLASH_BANK1_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash bank1 erase/program protection error flag */
#define FLASH_BANK2_OBF_FLAG ((uint32_t)0x10000001) /*!< flash bank2 operate busy flag */
#define FLASH_BANK2_ODF_FLAG ((uint32_t)0x10000020) /*!< flash bank2 operate done flag */
#define FLASH_BANK2_PRGMERR_FLAG ((uint32_t)0x10000004) /*!< flash bank2 program error flag */
#define FLASH_BANK2_EPPERR_FLAG ((uint32_t)0x10000010) /*!< flash bank2 erase/program protection error flag */
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
/**
* @brief flash interrupts
*/
#define FLASH_ERR_INT FLASH_BANK1_ERR_INT /*!< flash error interrupt */
#define FLASH_ODF_INT FLASH_BANK1_ODF_INT /*!< flash operate done interrupt */
#define FLASH_BANK1_ERR_INT ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
#define FLASH_BANK1_ODF_INT ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
#define FLASH_BANK2_ERR_INT ((uint32_t)0x00000004) /*!< flash bank2 error interrupt */
#define FLASH_BANK2_ODF_INT ((uint32_t)0x00000008) /*!< flash bank2 operate done interrupt */
/**
* @brief flash slib mask
*/
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib start sector */
#define FLASH_SLIB_INST_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib i-bus area start sector */
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFFF0000) /*!< flash slib end sector */
/**
* @brief user system data wdt_ato
*/
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
/**
* @brief user system data depslp_rst
*/
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
/**
* @brief user system data stdby_rst
*/
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
/**
* @brief user system data btopt
*/
#define FLASH_BOOT_FROM_BANK1 ((uint16_t)0x0008) /*!< boot from bank1 */
#define FLASH_BOOT_FROM_BANK2 ((uint16_t)0x0000) /*!< boot from bank 2 or bank 1,depending on the activation of the bank */
/**
* @brief user system data wdt_depslp
*/
#define USD_WDT_DEPSLP_CONTINUE ((uint16_t)0x0020) /*!< wdt continue count when entering in deepsleep */
#define USD_WDT_DEPSLP_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in deepsleep */
/**
* @brief user system data wdt_stdby
*/
#define USD_WDT_STDBY_CONTINUE ((uint16_t)0x0040) /*!< wdt continue count when entering in standby */
#define USD_WDT_STDBY_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in standby */
/**
* @brief flash timeout definition
*/
#define AT_ERASE_TIMEOUT ((uint32_t)0x80000000) /*!< internal flash erase operation timeout */
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
/**
* @brief set the flash clock divider definition
* @param div: the flash clock divider.
* this parameter can be one of the following values:
* - FLASH_CLOCK_DIV_2
* - FLASH_CLOCK_DIV_3
* - FLASH_CLOCK_DIV_4
*/
#define flash_clock_divider_set(div) (FLASH->divr_bit.fdiv = div)
/**
* @}
*/
/** @defgroup FLASH_exported_types
* @{
*/
/**
* @brief flash usd eopb0 type
*/
typedef enum
{
FLASH_EOPB0_SRAM_512K = 0x00, /*!< sram 512k, flash zw area 128k */
FLASH_EOPB0_SRAM_448K = 0x01, /*!< sram 448k, flash zw area 192k */
FLASH_EOPB0_SRAM_384K = 0x02, /*!< sram 384k, flash zw area 256k */
FLASH_EOPB0_SRAM_320K = 0x03, /*!< sram 320k, flash zw area 320k */
FLASH_EOPB0_SRAM_256K = 0x04, /*!< sram 256k, flash zw area 384k */
FLASH_EOPB0_SRAM_192K = 0x05, /*!< sram 192k, flash zw area 448k */
FLASH_EOPB0_SRAM_128K = 0x06 /*!< sram 128k, flash zw area 512k */
} flash_usd_eopb0_type;
/**
* @brief flash clock divider type
*/
typedef enum
{
FLASH_CLOCK_DIV_2 = 0x00, /*!< flash clock divide by 2 */
FLASH_CLOCK_DIV_3 = 0x01, /*!< flash clock divide by 3 */
FLASH_CLOCK_DIV_4 = 0x02 /*!< flash clock divide by 4 */
} flash_clock_divider_type;
/**
* @brief flash status type
*/
typedef enum
{
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
} flash_status_type;
/**
* @brief type define flash register all
*/
typedef struct
{
/**
* @brief flash psr register, offset:0x00
*/
union
{
__IO uint32_t psr;
struct
{
__IO uint32_t reserved1 : 12;/* [11:0] */
__IO uint32_t nzw_bst : 1; /* [12] */
__IO uint32_t nzw_bst_sts : 1; /* [13] */
__IO uint32_t reserved2 : 18;/* [31:14] */
} psr_bit;
};
/**
* @brief flash unlock register, offset:0x04
*/
union
{
__IO uint32_t unlock;
struct
{
__IO uint32_t ukval : 32;/* [31:0] */
} unlock_bit;
};
/**
* @brief flash usd unlock register, offset:0x08
*/
union
{
__IO uint32_t usd_unlock;
struct
{
__IO uint32_t usd_ukval : 32;/* [31:0] */
} usd_unlock_bit;
};
/**
* @brief flash sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts_bit;
};
/**
* @brief flash ctrl register, offset:0x10
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t bankers : 1; /* [2] */
__IO uint32_t blkers : 1; /* [3] */
__IO uint32_t usdprgm : 1; /* [4] */
__IO uint32_t usders : 1; /* [5] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved1 : 1; /* [8] */
__IO uint32_t usdulks : 1; /* [9] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved2 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved3 : 19;/* [31:13] */
} ctrl_bit;
};
/**
* @brief flash addr register, offset:0x14
*/
union
{
__IO uint32_t addr;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
} addr_bit;
};
/**
* @brief flash reserved1 register, offset:0x18
*/
__IO uint32_t reserved1;
/**
* @brief flash usd register, offset:0x1C
*/
union
{
__IO uint32_t usd;
struct
{
__IO uint32_t usderr : 1; /* [0] */
__IO uint32_t fap : 1; /* [1] */
__IO uint32_t wdt_ato_en : 1; /* [2] */
__IO uint32_t depslp_rst : 1; /* [3] */
__IO uint32_t stdby_rst : 1; /* [4] */
__IO uint32_t btopt : 1; /* [5] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t wdt_depslp : 1; /* [7] */
__IO uint32_t wdt_stdby : 1; /* [8] */
__IO uint32_t reserved2 : 1; /* [9] */
__IO uint32_t user_d0 : 8; /* [17:10] */
__IO uint32_t user_d1 : 8; /* [25:18] */
__IO uint32_t reserved3 : 6; /* [31:26] */
} usd_bit;
};
/**
* @brief flash epps0 register, offset:0x20
*/
union
{
__IO uint32_t epps0;
struct
{
__IO uint32_t epps : 32;/* [31:0] */
} epps0_bit;
};
/**
* @brief flash reserved2 register, offset:0x28~0x24
*/
__IO uint32_t reserved2[2];
/**
* @brief flash epps1 register, offset:0x2C
*/
union
{
__IO uint32_t epps1;
struct
{
__IO uint32_t epps : 32;/* [31:0] */
} epps1_bit;
};
/**
* @brief flash reserved3 register, offset:0x40~0x30
*/
__IO uint32_t reserved3[5];
/**
* @brief flash unlock2 register, offset:0x44
*/
union
{
__IO uint32_t unlock2;
struct
{
__IO uint32_t ukval : 32;/* [31:0] */
} unlock2_bit;
};
/**
* @brief flash reserved4 register, offset:0x48
*/
__IO uint32_t reserved4;
/**
* @brief flash sts2 register, offset:0x4C
*/
union
{
__IO uint32_t sts2;
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts2_bit;
};
/**
* @brief flash ctrl2 register, offset:0x50
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t bankers : 1; /* [2] */
__IO uint32_t blkers : 1; /* [3] */
__IO uint32_t reserved1 : 2; /* [5:4] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 2; /* [9:8] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 19;/* [31:13] */
} ctrl2_bit;
};
/**
* @brief flash addr2 register, offset:0x54
*/
union
{
__IO uint32_t addr2;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
} addr2_bit;
};
/**
* @brief flash contr register, offset:0x58
*/
union
{
__IO uint32_t contr;
struct
{
__IO uint32_t reserved1 : 31;/* [30:0] */
__IO uint32_t fcontr_en : 1; /* [31] */
} contr_bit;
};
/**
* @brief flash reserved5 register, offset:0x5C
*/
__IO uint32_t reserved5;
/**
* @brief flash divr register, offset:0x60
*/
union
{
__IO uint32_t divr;
struct
{
__IO uint32_t fdiv : 2; /* [1:0] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t fdiv_sts : 2; /* [5:4] */
__IO uint32_t reserved2 : 26;/* [31:6] */
} divr_bit;
};
/**
* @brief flash reserved6 register, offset:0xC4~0x64
*/
__IO uint32_t reserved6[25];
/**
* @brief flash slib_sts2 register, offset:0xC8
*/
union
{
__IO uint32_t slib_sts2;
struct
{
__IO uint32_t slib_inst_ss : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} slib_sts2_bit;
};
/**
* @brief flash slib_sts0 register, offset:0xCC
*/
union
{
__IO uint32_t slib_sts0;
struct
{
__IO uint32_t reserved1 : 3; /* [2:0] */
__IO uint32_t slib_enf : 1; /* [3] */
__IO uint32_t reserved2 : 28;/* [31:4] */
} slib_sts0_bit;
};
/**
* @brief flash slib_sts1 register, offset:0xD0
*/
union
{
__IO uint32_t slib_sts1;
struct
{
__IO uint32_t slib_ss : 16;/* [15:0] */
__IO uint32_t slib_es : 16;/* [31:16] */
} slib_sts1_bit;
};
/**
* @brief flash slib_pwd_clr register, offset:0xD4
*/
union
{
__IO uint32_t slib_pwd_clr;
struct
{
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
} slib_pwd_clr_bit;
};
/**
* @brief flash slib_misc_sts register, offset:0xD8
*/
union
{
__IO uint32_t slib_misc_sts;
struct
{
__IO uint32_t slib_pwd_err : 1; /* [0] */
__IO uint32_t slib_pwd_ok : 1; /* [1] */
__IO uint32_t slib_ulkf : 1; /* [2] */
__IO uint32_t reserved1 : 13;/* [15:3] */
__IO uint32_t slib_rcnt : 9; /* [24:16] */
__IO uint32_t reserved2 : 7; /* [31:25] */
} slib_misc_sts_bit;
};
/**
* @brief flash slib_set_pwd register, offset:0xDC
*/
union
{
__IO uint32_t slib_set_pwd;
struct
{
__IO uint32_t slib_pset_val : 32;/* [31:0] */
} slib_set_pwd_bit;
};
/**
* @brief flash slib_set_range0 register, offset:0xE0
*/
union
{
__IO uint32_t slib_set_range0;
struct
{
__IO uint32_t slib_ss_set : 16;/* [15:0] */
__IO uint32_t slib_es_set : 16;/* [31:16] */
} slib_set_range0_bit;
};
/**
* @brief flash slib_set_range1 register, offset:0xE4
*/
union
{
__IO uint32_t slib_set_range1;
struct
{
__IO uint32_t slib_iss_set : 16;/* [15:0] */
__IO uint32_t reserved1 : 15;/* [30:16] */
__IO uint32_t set_slib_strt : 1; /* [31] */
} slib_set_range1_bit;
};
/**
* @brief flash reserved7 register, offset:0xEC~0xE8
*/
__IO uint32_t reserved7[2];
/**
* @brief flash slib_unlock register, offset:0xF0
*/
union
{
__IO uint32_t slib_unlock;
struct
{
__IO uint32_t slib_ukval : 32;/* [31:0] */
} slib_unlock_bit;
};
/**
* @brief flash crc_ctrl register, offset:0xF4
*/
union
{
__IO uint32_t crc_ctrl;
struct
{
__IO uint32_t crc_ss : 12;/* [11:0] */
__IO uint32_t crc_sn : 12;/* [23:12] */
__IO uint32_t reserved1 : 7; /* [30:24] */
__IO uint32_t crc_strt : 1; /* [31] */
} crc_ctrl_bit;
};
/**
* @brief flash crc_chkr register, offset:0xF8
*/
union
{
__IO uint32_t crc_chkr;
struct
{
__IO uint32_t crc_chkr : 32;/* [31:0] */
} crc_chkr_bit;
};
} flash_type;
/**
* @brief user system data
*/
typedef struct
{
__IO uint16_t fap;
__IO uint16_t ssb;
__IO uint16_t data0;
__IO uint16_t data1;
__IO uint16_t epp0;
__IO uint16_t epp1;
__IO uint16_t epp2;
__IO uint16_t epp3;
__IO uint16_t eopb0;
__IO uint16_t reserved1;
__IO uint16_t epp4;
__IO uint16_t epp5;
__IO uint16_t epp6;
__IO uint16_t epp7;
__IO uint16_t reserved2[12];
__IO uint16_t qspikey[8];
} usd_type;
/**
* @}
*/
#define FLASH ((flash_type *) FLASH_REG_BASE)
#define USD ((usd_type *) USD_BASE)
/** @defgroup FLASH_exported_functions
* @{
*/
flag_status flash_flag_get(uint32_t flash_flag);
void flash_flag_clear(uint32_t flash_flag);
flash_status_type flash_operation_status_get(void);
flash_status_type flash_bank1_operation_status_get(void);
flash_status_type flash_bank2_operation_status_get(void);
flash_status_type flash_operation_wait_for(uint32_t time_out);
flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
void flash_unlock(void);
void flash_bank1_unlock(void);
void flash_bank2_unlock(void);
void flash_lock(void);
void flash_bank1_lock(void);
void flash_bank2_lock(void);
flash_status_type flash_sector_erase(uint32_t sector_address);
flash_status_type flash_block_erase(uint32_t block_address);
flash_status_type flash_internal_all_erase(void);
flash_status_type flash_bank1_erase(void);
flash_status_type flash_bank2_erase(void);
flash_status_type flash_user_system_data_erase(void);
flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
flash_status_type flash_word_program(uint32_t address, uint32_t data);
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
flash_status_type flash_epp_set(uint32_t *sector_bits);
void flash_epp_status_get(uint32_t *sector_bits);
flash_status_type flash_fap_enable(confirm_state new_state);
flag_status flash_fap_status_get(void);
flash_status_type flash_ssb_set(uint8_t usd_ssb);
uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
uint32_t flash_slib_remaining_count_get(void);
flag_status flash_slib_state_get(void);
uint16_t flash_slib_start_sector_get(void);
uint16_t flash_slib_inststart_sector_get(void);
uint16_t flash_slib_end_sector_get(void);
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
void flash_nzw_boost_enable(confirm_state new_state);
void flash_continue_read_enable(confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_gpio.h Normal file
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@ -0,0 +1,565 @@
/**
**************************************************************************
* @file at32f435_437_gpio.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_GPIO_H
#define __AT32F435_437_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_pins_number_definition
* @{
*/
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
/**
* @}
*/
/** @defgroup GPIO_exported_types
* @{
*/
/**
* @brief gpio mode select
*/
typedef enum
{
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
} gpio_mode_type;
/**
* @brief gpio output drive strength select
*/
typedef enum
{
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
} gpio_drive_type;
/**
* @brief gpio output type
*/
typedef enum
{
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
} gpio_output_type;
/**
* @brief gpio pull type
*/
typedef enum
{
GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
GPIO_PULL_UP = 0x01, /*!< pull-up */
GPIO_PULL_DOWN = 0x02 /*!< pull-down */
} gpio_pull_type;
/**
* @brief gpio init type
*/
typedef struct
{
uint32_t gpio_pins; /*!< pins number selection */
gpio_output_type gpio_out_type; /*!< output type selection */
gpio_pull_type gpio_pull; /*!< pull type selection */
gpio_mode_type gpio_mode; /*!< mode selection */
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
} gpio_init_type;
/**
* @brief gpio pins source type
*/
typedef enum
{
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
} gpio_pins_source_type;
/**
* @brief gpio muxing function selection type
*/
typedef enum
{
GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
} gpio_mux_sel_type;
/**
* @brief type define gpio register all
*/
typedef struct
{
/**
* @brief gpio mode register, offset:0x00
*/
union
{
__IO uint32_t cfgr;
struct
{
__IO uint32_t iomc0 : 2; /* [1:0] */
__IO uint32_t iomc1 : 2; /* [3:2] */
__IO uint32_t iomc2 : 2; /* [5:4] */
__IO uint32_t iomc3 : 2; /* [7:6] */
__IO uint32_t iomc4 : 2; /* [9:8] */
__IO uint32_t iomc5 : 2; /* [11:10] */
__IO uint32_t iomc6 : 2; /* [13:12] */
__IO uint32_t iomc7 : 2; /* [15:14] */
__IO uint32_t iomc8 : 2; /* [17:16] */
__IO uint32_t iomc9 : 2; /* [19:18] */
__IO uint32_t iomc10 : 2; /* [21:20] */
__IO uint32_t iomc11 : 2; /* [23:22] */
__IO uint32_t iomc12 : 2; /* [25:24] */
__IO uint32_t iomc13 : 2; /* [27:26] */
__IO uint32_t iomc14 : 2; /* [29:28] */
__IO uint32_t iomc15 : 2; /* [31:30] */
} cfgr_bit;
};
/**
* @brief gpio output type register, offset:0x04
*/
union
{
__IO uint32_t omode;
struct
{
__IO uint32_t om0 : 1; /* [0] */
__IO uint32_t om1 : 1; /* [1] */
__IO uint32_t om2 : 1; /* [2] */
__IO uint32_t om3 : 1; /* [3] */
__IO uint32_t om4 : 1; /* [4] */
__IO uint32_t om5 : 1; /* [5] */
__IO uint32_t om6 : 1; /* [6] */
__IO uint32_t om7 : 1; /* [7] */
__IO uint32_t om8 : 1; /* [8] */
__IO uint32_t om9 : 1; /* [9] */
__IO uint32_t om10 : 1; /* [10] */
__IO uint32_t om11 : 1; /* [11] */
__IO uint32_t om12 : 1; /* [12] */
__IO uint32_t om13 : 1; /* [13] */
__IO uint32_t om14 : 1; /* [14] */
__IO uint32_t om15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} omode_bit;
};
/**
* @brief gpio output driver register, offset:0x08
*/
union
{
__IO uint32_t odrvr;
struct
{
__IO uint32_t odrv0 : 2; /* [1:0] */
__IO uint32_t odrv1 : 2; /* [3:2] */
__IO uint32_t odrv2 : 2; /* [5:4] */
__IO uint32_t odrv3 : 2; /* [7:6] */
__IO uint32_t odrv4 : 2; /* [9:8] */
__IO uint32_t odrv5 : 2; /* [11:10] */
__IO uint32_t odrv6 : 2; /* [13:12] */
__IO uint32_t odrv7 : 2; /* [15:14] */
__IO uint32_t odrv8 : 2; /* [17:16] */
__IO uint32_t odrv9 : 2; /* [19:18] */
__IO uint32_t odrv10 : 2; /* [21:20] */
__IO uint32_t odrv11 : 2; /* [23:22] */
__IO uint32_t odrv12 : 2; /* [25:24] */
__IO uint32_t odrv13 : 2; /* [27:26] */
__IO uint32_t odrv14 : 2; /* [29:28] */
__IO uint32_t odrv15 : 2; /* [31:30] */
} odrvr_bit;
};
/**
* @brief gpio pull up/down register, offset:0x0C
*/
union
{
__IO uint32_t pull;
struct
{
__IO uint32_t pull0 : 2; /* [1:0] */
__IO uint32_t pull1 : 2; /* [3:2] */
__IO uint32_t pull2 : 2; /* [5:4] */
__IO uint32_t pull3 : 2; /* [7:6] */
__IO uint32_t pull4 : 2; /* [9:8] */
__IO uint32_t pull5 : 2; /* [11:10] */
__IO uint32_t pull6 : 2; /* [13:12] */
__IO uint32_t pull7 : 2; /* [15:14] */
__IO uint32_t pull8 : 2; /* [17:16] */
__IO uint32_t pull9 : 2; /* [19:18] */
__IO uint32_t pull10 : 2; /* [21:20] */
__IO uint32_t pull11 : 2; /* [23:22] */
__IO uint32_t pull12 : 2; /* [25:24] */
__IO uint32_t pull13 : 2; /* [27:26] */
__IO uint32_t pull14 : 2; /* [29:28] */
__IO uint32_t pull15 : 2; /* [31:30] */
} pull_bit;
};
/**
* @brief gpio input data register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt0 : 1; /* [0] */
__IO uint32_t idt1 : 1; /* [1] */
__IO uint32_t idt2 : 1; /* [2] */
__IO uint32_t idt3 : 1; /* [3] */
__IO uint32_t idt4 : 1; /* [4] */
__IO uint32_t idt5 : 1; /* [5] */
__IO uint32_t idt6 : 1; /* [6] */
__IO uint32_t idt7 : 1; /* [7] */
__IO uint32_t idt8 : 1; /* [8] */
__IO uint32_t idt9 : 1; /* [9] */
__IO uint32_t idt10 : 1; /* [10] */
__IO uint32_t idt11 : 1; /* [11] */
__IO uint32_t idt12 : 1; /* [12] */
__IO uint32_t idt13 : 1; /* [13] */
__IO uint32_t idt14 : 1; /* [14] */
__IO uint32_t idt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} idt_bit;
};
/**
* @brief gpio output data register, offset:0x14
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt0 : 1; /* [0] */
__IO uint32_t odt1 : 1; /* [1] */
__IO uint32_t odt2 : 1; /* [2] */
__IO uint32_t odt3 : 1; /* [3] */
__IO uint32_t odt4 : 1; /* [4] */
__IO uint32_t odt5 : 1; /* [5] */
__IO uint32_t odt6 : 1; /* [6] */
__IO uint32_t odt7 : 1; /* [7] */
__IO uint32_t odt8 : 1; /* [8] */
__IO uint32_t odt9 : 1; /* [9] */
__IO uint32_t odt10 : 1; /* [10] */
__IO uint32_t odt11 : 1; /* [11] */
__IO uint32_t odt12 : 1; /* [12] */
__IO uint32_t odt13 : 1; /* [13] */
__IO uint32_t odt14 : 1; /* [14] */
__IO uint32_t odt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} odt_bit;
};
/**
* @brief gpio scr register, offset:0x18
*/
union
{
__IO uint32_t scr;
struct
{
__IO uint32_t iosb0 : 1; /* [0] */
__IO uint32_t iosb1 : 1; /* [1] */
__IO uint32_t iosb2 : 1; /* [2] */
__IO uint32_t iosb3 : 1; /* [3] */
__IO uint32_t iosb4 : 1; /* [4] */
__IO uint32_t iosb5 : 1; /* [5] */
__IO uint32_t iosb6 : 1; /* [6] */
__IO uint32_t iosb7 : 1; /* [7] */
__IO uint32_t iosb8 : 1; /* [8] */
__IO uint32_t iosb9 : 1; /* [9] */
__IO uint32_t iosb10 : 1; /* [10] */
__IO uint32_t iosb11 : 1; /* [11] */
__IO uint32_t iosb12 : 1; /* [12] */
__IO uint32_t iosb13 : 1; /* [13] */
__IO uint32_t iosb14 : 1; /* [14] */
__IO uint32_t iosb15 : 1; /* [15] */
__IO uint32_t iocb0 : 1; /* [16] */
__IO uint32_t iocb1 : 1; /* [17] */
__IO uint32_t iocb2 : 1; /* [18] */
__IO uint32_t iocb3 : 1; /* [19] */
__IO uint32_t iocb4 : 1; /* [20] */
__IO uint32_t iocb5 : 1; /* [21] */
__IO uint32_t iocb6 : 1; /* [22] */
__IO uint32_t iocb7 : 1; /* [23] */
__IO uint32_t iocb8 : 1; /* [24] */
__IO uint32_t iocb9 : 1; /* [25] */
__IO uint32_t iocb10 : 1; /* [26] */
__IO uint32_t iocb11 : 1; /* [27] */
__IO uint32_t iocb12 : 1; /* [28] */
__IO uint32_t iocb13 : 1; /* [29] */
__IO uint32_t iocb14 : 1; /* [30] */
__IO uint32_t iocb15 : 1; /* [31] */
} scr_bit;
};
/**
* @brief gpio wpen register, offset:0x1C
*/
union
{
__IO uint32_t wpr;
struct
{
__IO uint32_t wpen0 : 1; /* [0] */
__IO uint32_t wpen1 : 1; /* [1] */
__IO uint32_t wpen2 : 1; /* [2] */
__IO uint32_t wpen3 : 1; /* [3] */
__IO uint32_t wpen4 : 1; /* [4] */
__IO uint32_t wpen5 : 1; /* [5] */
__IO uint32_t wpen6 : 1; /* [6] */
__IO uint32_t wpen7 : 1; /* [7] */
__IO uint32_t wpen8 : 1; /* [8] */
__IO uint32_t wpen9 : 1; /* [9] */
__IO uint32_t wpen10 : 1; /* [10] */
__IO uint32_t wpen11 : 1; /* [11] */
__IO uint32_t wpen12 : 1; /* [12] */
__IO uint32_t wpen13 : 1; /* [13] */
__IO uint32_t wpen14 : 1; /* [14] */
__IO uint32_t wpen15 : 1; /* [15] */
__IO uint32_t wpseq : 1; /* [16] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} wpr_bit;
};
/**
* @brief gpio muxl register, offset:0x20
*/
union
{
__IO uint32_t muxl;
struct
{
__IO uint32_t muxl0 : 4; /* [3:0] */
__IO uint32_t muxl1 : 4; /* [7:4] */
__IO uint32_t muxl2 : 4; /* [11:8] */
__IO uint32_t muxl3 : 4; /* [15:12] */
__IO uint32_t muxl4 : 4; /* [19:16] */
__IO uint32_t muxl5 : 4; /* [23:20] */
__IO uint32_t muxl6 : 4; /* [27:24] */
__IO uint32_t muxl7 : 4; /* [31:28] */
} muxl_bit;
};
/**
* @brief gpio muxh register, offset:0x24
*/
union
{
__IO uint32_t muxh;
struct
{
__IO uint32_t muxh8 : 4; /* [3:0] */
__IO uint32_t muxh9 : 4; /* [7:4] */
__IO uint32_t muxh10 : 4; /* [11:8] */
__IO uint32_t muxh11 : 4; /* [15:12] */
__IO uint32_t muxh12 : 4; /* [19:16] */
__IO uint32_t muxh13 : 4; /* [23:20] */
__IO uint32_t muxh14 : 4; /* [27:24] */
__IO uint32_t muxh15 : 4; /* [31:28] */
} muxh_bit;
};
/**
* @brief gpio clr register, offset:0x28
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t iocb0 : 1; /* [0] */
__IO uint32_t iocb1 : 1; /* [1] */
__IO uint32_t iocb2 : 1; /* [2] */
__IO uint32_t iocb3 : 1; /* [3] */
__IO uint32_t iocb4 : 1; /* [4] */
__IO uint32_t iocb5 : 1; /* [5] */
__IO uint32_t iocb6 : 1; /* [6] */
__IO uint32_t iocb7 : 1; /* [7] */
__IO uint32_t iocb8 : 1; /* [8] */
__IO uint32_t iocb9 : 1; /* [9] */
__IO uint32_t iocb10 : 1; /* [10] */
__IO uint32_t iocb11 : 1; /* [11] */
__IO uint32_t iocb12 : 1; /* [12] */
__IO uint32_t iocb13 : 1; /* [13] */
__IO uint32_t iocb14 : 1; /* [14] */
__IO uint32_t iocb15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} clr_bit;
};
/**
* @brief gpio reserved1 register, offset:0x2C~0x38
*/
__IO uint32_t reserved1[4];
/**
* @brief gpio hdrv register, offset:0x3C
*/
union
{
__IO uint32_t hdrv;
struct
{
__IO uint32_t hdrv0 : 1; /* [0] */
__IO uint32_t hdrv1 : 1; /* [1] */
__IO uint32_t hdrv2 : 1; /* [2] */
__IO uint32_t hdrv3 : 1; /* [3] */
__IO uint32_t hdrv4 : 1; /* [4] */
__IO uint32_t hdrv5 : 1; /* [5] */
__IO uint32_t hdrv6 : 1; /* [6] */
__IO uint32_t hdrv7 : 1; /* [7] */
__IO uint32_t hdrv8 : 1; /* [8] */
__IO uint32_t hdrv9 : 1; /* [9] */
__IO uint32_t hdrv10 : 1; /* [10] */
__IO uint32_t hdrv11 : 1; /* [11] */
__IO uint32_t hdrv12 : 1; /* [12] */
__IO uint32_t hdrv13 : 1; /* [13] */
__IO uint32_t hdrv14 : 1; /* [14] */
__IO uint32_t hdrv15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} hdrv_bit;
};
} gpio_type;
/**
* @}
*/
#define GPIOA ((gpio_type *) GPIOA_BASE)
#define GPIOB ((gpio_type *) GPIOB_BASE)
#define GPIOC ((gpio_type *) GPIOC_BASE)
#define GPIOD ((gpio_type *) GPIOD_BASE)
#define GPIOE ((gpio_type *) GPIOE_BASE)
#define GPIOF ((gpio_type *) GPIOF_BASE)
#define GPIOG ((gpio_type *) GPIOG_BASE)
#define GPIOH ((gpio_type *) GPIOH_BASE)
/** @defgroup GPIO_exported_functions
* @{
*/
void gpio_reset(gpio_type *gpio_x);
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_input_data_read(gpio_type *gpio_x);
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

479
lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_i2c.h Normal file
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@ -0,0 +1,479 @@
/**
**************************************************************************
* @file at32f435_437_i2c.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 i2c header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_I2C_H
#define __AT32F435_437_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/**
* @brief maximum number of single transfers
*/
#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
* @{
*/
#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @brief i2c flag
* @{
*/
#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
/**
* @}
*/
/** @defgroup I2C_exported_types
* @{
*/
/**
* @brief i2c smbus mode set
*/
typedef enum
{
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
} i2c_smbus_mode_type;
/**
* @brief i2c address mode
*/
typedef enum
{
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
} i2c_address_mode_type;
/**
* @brief i2c transfer direction
*/
typedef enum
{
I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
} i2c_transfer_dir_type;
/**
* @brief i2c dma requests direction
*/
typedef enum
{
I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
} i2c_dma_request_type;
/**
* @brief i2c smbus alert pin set
*/
typedef enum
{
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
} i2c_smbus_alert_set_type;
/**
* @brief i2c clock timeout detection mode
*/
typedef enum
{
I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
} i2c_timeout_detcet_type;
/**
* @brief i2c own address2 mask
*/
typedef enum
{
I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
} i2c_addr2_mask_type;
/**
* @brief i2c reload end mode
*/
typedef enum
{
I2C_AUTO_STOP_MODE = 0x02000000, /*!< auto generate stop mode */
I2C_SOFT_STOP_MODE = 0x00000000, /*!< soft generate stop mode */
I2C_RELOAD_MODE = 0x01000000 /*!< reload mode */
} i2c_reload_stop_mode_type;
/**
* @brief i2c start mode
*/
typedef enum
{
I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */
I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */
I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */
} i2c_start_mode_type;
/**
* @brief type define i2c register all
*/
typedef struct
{
/**
* @brief i2c ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t i2cen : 1; /* [0] */
__IO uint32_t tdien : 1; /* [1] */
__IO uint32_t rdien : 1; /* [2] */
__IO uint32_t addrien : 1; /* [3] */
__IO uint32_t ackfailien : 1; /* [4] */
__IO uint32_t stopien : 1; /* [5] */
__IO uint32_t tdcien : 1; /* [6] */
__IO uint32_t errien : 1; /* [7] */
__IO uint32_t dflt : 4; /* [11:8] */
__IO uint32_t reserved1 : 2; /* [13:12] */
__IO uint32_t dmaten : 1; /* [14] */
__IO uint32_t dmaren : 1; /* [15] */
__IO uint32_t sctrl : 1; /* [16] */
__IO uint32_t stretch : 1; /* [17] */
__IO uint32_t reserved2 : 1; /* [18] */
__IO uint32_t gcaen : 1; /* [19] */
__IO uint32_t haddren : 1; /* [20] */
__IO uint32_t devaddren : 1; /* [21] */
__IO uint32_t smbalert : 1; /* [22] */
__IO uint32_t pecen : 1; /* [23] */
__IO uint32_t reserved3 : 8; /* [31:24] */
} ctrl1_bit;
};
/**
* @brief i2c ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t saddr : 10;/* [9:0] */
__IO uint32_t dir : 1; /* [10] */
__IO uint32_t addr10 : 1; /* [11] */
__IO uint32_t readh10 : 1; /* [12] */
__IO uint32_t genstart : 1; /* [13] */
__IO uint32_t genstop : 1; /* [14] */
__IO uint32_t nacken : 1; /* [15] */
__IO uint32_t cnt : 8; /* [23:16] */
__IO uint32_t rlden : 1; /* [24] */
__IO uint32_t astopen : 1; /* [25] */
__IO uint32_t pecten : 1; /* [26] */
__IO uint32_t reserved1 : 5; /* [31:27] */
} ctrl2_bit;
};
/**
* @brief i2c oaddr1 register, offset:0x08
*/
union
{
__IO uint32_t oaddr1;
struct
{
__IO uint32_t addr1 : 10;/* [9:0] */
__IO uint32_t addr1mode : 1; /* [10] */
__IO uint32_t reserved1 : 4; /* [14:11] */
__IO uint32_t addr1en : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} oaddr1_bit;
};
/**
* @brief i2c oaddr2 register, offset:0x0c
*/
union
{
__IO uint32_t oaddr2;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t addr2 : 7; /* [7:1] */
__IO uint32_t addr2mask : 3; /* [10:8] */
__IO uint32_t reserved2 : 4; /* [14:11] */
__IO uint32_t addr2en : 1; /* [15] */
__IO uint32_t reserved3 : 16;/* [31:16] */
} oaddr2_bit;
};
/**
* @brief i2c clkctrl register, offset:0x10
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t scll : 8; /* [7:0] */
__IO uint32_t sclh : 8; /* [15:8] */
__IO uint32_t sdad : 4; /* [19:16] */
__IO uint32_t scld : 4; /* [23:20] */
__IO uint32_t divh : 4; /* [27:24] */
__IO uint32_t divl : 4; /* [31:28] */
} clkctrl_bit;
};
/**
* @brief i2c timeout register, offset:0x14
*/
union
{
__IO uint32_t timeout;
struct
{
__IO uint32_t totime : 12;/* [11:0] */
__IO uint32_t tomode : 1; /* [12] */
__IO uint32_t reserved1 : 2; /* [14:13] */
__IO uint32_t toen : 1; /* [15] */
__IO uint32_t exttime : 12;/* [27:16] */
__IO uint32_t reserved2 : 3; /* [30:28] */
__IO uint32_t exten : 1; /* [31] */
} timeout_bit;
};
/**
* @brief i2c sts register, offset:0x18
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t tdbe : 1; /* [0] */
__IO uint32_t tdis : 1; /* [1] */
__IO uint32_t rdbf : 1; /* [2] */
__IO uint32_t addrf : 1; /* [3] */
__IO uint32_t ackfail : 1; /* [4] */
__IO uint32_t stopf : 1; /* [5] */
__IO uint32_t tdc : 1; /* [6] */
__IO uint32_t tcrld : 1; /* [7] */
__IO uint32_t buserr : 1; /* [8] */
__IO uint32_t arlost : 1; /* [9] */
__IO uint32_t ouf : 1; /* [10] */
__IO uint32_t pecerr : 1; /* [11] */
__IO uint32_t tmout : 1; /* [12] */
__IO uint32_t alertf : 1; /* [13] */
__IO uint32_t reserved1 : 1; /* [14] */
__IO uint32_t busyf : 1; /* [15] */
__IO uint32_t sdir : 1; /* [16] */
__IO uint32_t addr : 7; /* [23:17] */
__IO uint32_t reserved2 : 8; /* [31:24] */
} sts_bit;
};
/**
* @brief i2c clr register, offset:0x1c
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t reserved1 : 3; /* [2:0] */
__IO uint32_t addrc : 1; /* [3] */
__IO uint32_t ackfailc : 1; /* [4] */
__IO uint32_t stopc : 1; /* [5] */
__IO uint32_t reserved2 : 2; /* [6:7] */
__IO uint32_t buserrc : 1; /* [8] */
__IO uint32_t arlostc : 1; /* [9] */
__IO uint32_t oufc : 1; /* [10] */
__IO uint32_t pecerrc : 1; /* [11] */
__IO uint32_t tmoutc : 1; /* [12] */
__IO uint32_t alertc : 1; /* [13] */
__IO uint32_t reserved3 : 18;/* [31:14] */
} clr_bit;
};
/**
* @brief i2c pec register, offset:0x20
*/
union
{
__IO uint32_t pec;
struct
{
__IO uint32_t pecval : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} pec_bit;
};
/**
* @brief i2c rxdt register, offset:0x20
*/
union
{
__IO uint32_t rxdt;
struct
{
__IO uint32_t dt : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} rxdt_bit;
};
/**
* @brief i2c txdt register, offset:0x20
*/
union
{
__IO uint32_t txdt;
struct
{
__IO uint32_t dt : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} txdt_bit;
};
} i2c_type;
/**
* @}
*/
#define I2C1 ((i2c_type *) I2C1_BASE)
#define I2C2 ((i2c_type *) I2C2_BASE)
#define I2C3 ((i2c_type *) I2C3_BASE)
/** @defgroup I2C_exported_functions
* @{
*/
void i2c_reset(i2c_type *i2c_x);
void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
void i2c_start_generate(i2c_type *i2c_x);
void i2c_stop_generate(i2c_type *i2c_x);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
uint8_t i2c_data_receive(i2c_type *i2c_x);
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_misc.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 misc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_MISC_H
#define __AT32F435_437_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_vector_table_base_address
* @{
*/
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
/**
* @}
*/
/** @defgroup MISC_exported_types
* @{
*/
/**
* @brief nvic interrupt priority group
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
} nvic_priority_group_type;
/**
* @brief nvic low power mode
*/
typedef enum
{
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
} nvic_lowpower_mode_type;
/**
* @brief systick clock source
*/
typedef enum
{
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
} systick_clock_source_type;
/**
* @}
*/
/** @defgroup MISC_exported_functions
* @{
*/
void nvic_system_reset(void);
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(IRQn_Type irqn);
void nvic_priority_group_config(nvic_priority_group_type priority_group);
void nvic_vector_table_set(uint32_t base, uint32_t offset);
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
void systick_clock_source_config(systick_clock_source_type source);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_pwc.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 pwr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_PWC_H
#define __AT32F435_437_PWC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup PWC
* @{
*/
/** @defgroup PWC_flags_definition
* @brief pwc flag
* @{
*/
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
/**
* @}
*/
/**
* @brief pwc wakeup pin num definition
*/
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */
/**
* @brief select ldo output voltage.
* @param val: set the ldo output voltage.
* this parameter can be one of the following values:
* - PWC_LDO_OUTPUT_1V3: system clock up to 288MHz.
* - PWC_LDO_OUTPUT_1V2: system clock up to 240MHz.
* - PWC_LDO_OUTPUT_1V1: system clock up to 192MHz.
* - PWC_LDO_OUTPUT_1V0: system clock up to 144MHz.
* @note useage limited.
* PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V.
*/
#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
/** @defgroup PWC_exported_types
* @{
*/
/**
* @brief pwc pvm voltage type
*/
typedef enum
{
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
} pwc_pvm_voltage_type;
/**
* @brief pwc ldo output voltage type
*/
typedef enum
{
PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
} pwc_ldo_output_voltage_type;
/**
* @brief pwc sleep enter type
*/
typedef enum
{
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
} pwc_sleep_enter_type ;
/**
* @brief pwc deep sleep enter type
*/
typedef enum
{
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
} pwc_deep_sleep_enter_type ;
/**
* @brief pwc regulator type
*/
typedef enum
{
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
} pwc_regulator_type ;
/**
* @brief type define pwc register all
*/
typedef struct
{
/**
* @brief pwc ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t vrsel : 1; /* [0] */
__IO uint32_t lpsel : 1; /* [1] */
__IO uint32_t clswef : 1; /* [2] */
__IO uint32_t clsef : 1; /* [3] */
__IO uint32_t pvmen : 1; /* [4] */
__IO uint32_t pvmsel : 3; /* [7:5] */
__IO uint32_t bpwen : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} ctrl_bit;
};
/**
* @brief pwc ctrlsts register, offset:0x04
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t swef : 1; /* [0] */
__IO uint32_t sef : 1; /* [1] */
__IO uint32_t pvmof : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t swpen1 : 1; /* [8] */
__IO uint32_t swpen2 : 1; /* [9] */
__IO uint32_t reserved2 : 22;/* [31:10] */
} ctrlsts_bit;
};
__IO uint32_t reserved1[2];
/**
* @brief pwc ldoov register, offset:0x10
*/
union
{
__IO uint32_t ldoov;
struct
{
__IO uint32_t ldoovsel : 3; /* [2:0] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} ldoov_bit;
};
} pwc_type;
/**
* @}
*/
#define PWC ((pwc_type *) PWC_BASE)
/** @defgroup PWC_exported_functions
* @{
*/
void pwc_reset(void);
void pwc_battery_powered_domain_access(confirm_state new_state);
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
void pwc_power_voltage_monitor_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
void pwc_flag_clear(uint32_t pwc_flag);
flag_status pwc_flag_get(uint32_t pwc_flag);
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
void pwc_standby_mode_enter(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_qspi.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 qspi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_QSPI_H
#define __AT32F435_437_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup QSPI
* @{
*/
/** @defgroup QSPI_flags_definition
* @brief qspi flag
* @{
*/
#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
/**
* @}
*/
/** @defgroup QSPI_exported_types
* @{
*/
/**
* @brief qspi xip read access mode type
*/
typedef enum
{
QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
} qspi_xip_read_sel_type;
/**
* @brief qspi xip write access mode type
*/
typedef enum
{
QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
} qspi_xip_write_sel_type;
/**
* @brief qspi busy bit offset position in status register type
*/
typedef enum
{
QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
} qspi_busy_pos_type;
/**
* @brief qspi read status configure type
*/
typedef enum
{
QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
} qspi_read_status_conf_type;
/**
* @brief qspi operate mode type
*/
typedef enum
{
QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
} qspi_operate_mode_type;
/**
* @brief qspi clock division type
*/
typedef enum
{
QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
} qspi_clk_div_type;
/**
* @brief qspi command port address length type
*/
typedef enum
{
QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
} qspi_cmd_adrlen_type;
/**
* @brief qspi command port instruction length type
*/
typedef enum
{
QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
} qspi_cmd_inslen_type;
/**
* @brief qspi xip r/w address length type
*/
typedef enum
{
QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
} qspi_xip_addrlen_type;
/**
* @brief qspi sckout mode type
*/
typedef enum
{
QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
} qspi_clk_mode_type;
/**
* @brief qspi dma tx/rx fifo threshold type
*/
typedef enum
{
QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
} qspi_dma_fifo_thod_type;
/**
* @brief qspi cmd type
*/
typedef struct
{
confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
uint8_t instruction_code; /*!< instruction code */
qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
uint32_t address_code; /*!< address code */
qspi_cmd_adrlen_type address_length; /*!< address legnth */
uint32_t data_counter; /*!< read/write data counter */
uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
qspi_operate_mode_type operation_mode; /*!< operation mode */
qspi_read_status_conf_type read_status_config; /*!< config to read status */
confirm_state read_status_enable; /*!< config to read status */
confirm_state write_data_enable; /*!< enable to write data */
} qspi_cmd_type;
/**
* @brief qspi xip type
*/
typedef struct
{
uint8_t read_instruction_code; /*!< read instruction code */
qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
uint8_t write_instruction_code; /*!< write instruction code */
qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
uint8_t write_time_counter; /*!< write count for mode t */
uint8_t write_data_counter; /*!< write count for mode d */
qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
uint8_t read_time_counter; /*!< read count for mode t */
uint8_t read_data_counter; /*!< read count for mode d */
} qspi_xip_type;
/**
* @brief type define qspi register all
*/
typedef struct
{
/**
* @brief qspi cmd_w0 register, offset:0x00
*/
union
{
__IO uint32_t cmd_w0;
struct
{
__IO uint32_t spiadr : 32;/* [31:0] */
} cmd_w0_bit;
};
/**
* @brief qspi cmd_w1 register, offset:0x04
*/
union
{
__IO uint32_t cmd_w1;
struct
{
__IO uint32_t adrlen : 3; /* [2:0] */
__IO uint32_t reserved1 : 13;/* [15:3] */
__IO uint32_t dum2 : 8; /* [23:16] */
__IO uint32_t inslen : 2; /* [25:24] */
__IO uint32_t reserved2 : 2; /* [27:26] */
__IO uint32_t pemen : 1; /* [28] */
__IO uint32_t reserved3 : 3; /* [31:29] */
} cmd_w1_bit;
};
/**
* @brief qspi cmd_w2 register, offset:0x08
*/
union
{
__IO uint32_t cmd_w2;
struct
{
__IO uint32_t dcnt : 32;/* [31:0] */
} cmd_w2_bit;
};
/**
* @brief qspi cmd_w3 register, offset:0x0C
*/
union
{
__IO uint32_t cmd_w3;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t wen : 1; /* [1] */
__IO uint32_t rstsen : 1; /* [2] */
__IO uint32_t rstsc : 1; /* [3] */
__IO uint32_t reserved2 : 1; /* [4] */
__IO uint32_t opmode : 3; /* [7:5] */
__IO uint32_t reserved3 : 8; /* [15:8] */
__IO uint32_t pemopc : 8; /* [23:16] */
__IO uint32_t insc : 8; /* [31:24] */
} cmd_w3_bit;
};
/**
* @brief qspi ctrl register, offset:0x10
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t clkdiv : 3; /* [2:0] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t sckmode : 1; /* [4] */
__IO uint32_t reserved2 : 2; /* [6:5] */
__IO uint32_t xipidle : 1; /* [7] */
__IO uint32_t abort : 1; /* [8] */
__IO uint32_t reserved3 : 7; /* [15:9] */
__IO uint32_t busy : 3; /* [18:16] */
__IO uint32_t xiprcmdf : 1; /* [19] */
__IO uint32_t xipsel : 1; /* [20] */
__IO uint32_t keyen : 1; /* [21] */
__IO uint32_t reserved4 : 10;/* [31:22] */
} ctrl_bit;
};
/**
* @brief qspi actr register, offset:0x14
*/
union
{
__IO uint32_t actr;
struct
{
__IO uint32_t csdly : 4; /* [3:0] */
__IO uint32_t reserved1 : 28;/* [31:4] */
} actr_bit;
};
/**
* @brief qspi fifosts register, offset:0x18
*/
union
{
__IO uint32_t fifosts;
struct
{
__IO uint32_t txfifordy : 1; /* [0] */
__IO uint32_t rxfifordy : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} fifosts_bit;
};
/**
* @brief qspi reserved register, offset:0x1C
*/
__IO uint32_t reserved1;
/**
* @brief qspi ctrl2 register, offset:0x20
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t dmaen : 1; /* [0] */
__IO uint32_t cmdie : 1; /* [1] */
__IO uint32_t reserved1 : 6; /* [7:2] */
__IO uint32_t txfifo_thod : 2; /* [9:8] */
__IO uint32_t reserved2 : 2; /* [11:10] */
__IO uint32_t rxfifo_thod : 2; /* [13:12] */
__IO uint32_t reserved3 : 18;/* [31:14] */
} ctrl2_bit;
};
/**
* @brief qspi cmdsts register, offset:0x24
*/
union
{
__IO uint32_t cmdsts;
struct
{
__IO uint32_t cmdsts : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} cmdsts_bit;
};
/**
* @brief qspi rsts register, offset:0x28
*/
union
{
__IO uint32_t rsts;
struct
{
__IO uint32_t spists : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} rsts_bit;
};
/**
* @brief qspi fsize register, offset:0x2C
*/
union
{
__IO uint32_t fsize;
struct
{
__IO uint32_t spifsize : 32;/* [31:0] */
} fsize_bit;
};
/**
* @brief qspi xip_cmd_w0 register, offset:0x30
*/
union
{
__IO uint32_t xip_cmd_w0;
struct
{
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
__IO uint32_t xipr_opmode : 3; /* [10:8] */
__IO uint32_t xipr_adrlen : 1; /* [11] */
__IO uint32_t xipr_insc : 8; /* [19:12] */
__IO uint32_t reserved1 : 12;/* [31:20] */
} xip_cmd_w0_bit;
};
/**
* @brief qspi xip_cmd_w1 register, offset:0x34
*/
union
{
__IO uint32_t xip_cmd_w1;
struct
{
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
__IO uint32_t xipr_opmode : 3; /* [10:8] */
__IO uint32_t xipr_adrlen : 1; /* [11] */
__IO uint32_t xipr_insc : 8; /* [19:12] */
__IO uint32_t reserved1 : 12;/* [31:20] */
} xip_cmd_w1_bit;
};
/**
* @brief qspi xip_cmd_w2 register, offset:0x38
*/
union
{
__IO uint32_t xip_cmd_w2;
struct
{
__IO uint32_t xipr_dcnt : 6; /* [5:0] */
__IO uint32_t reserved1 : 2; /* [7:6] */
__IO uint32_t xipr_tcnt : 7; /* [14:8] */
__IO uint32_t xipr_sel : 1; /* [15] */
__IO uint32_t xipw_dcnt : 6; /* [21:16] */
__IO uint32_t reserved2 : 2; /* [23:22] */
__IO uint32_t xipw_tcnt : 7; /* [30:24] */
__IO uint32_t xipw_sel : 1; /* [31] */
} xip_cmd_w2_bit;
};
/**
* @brief qspi xip_cmd_w3 register, offset:0x3C
*/
union
{
__IO uint32_t xip_cmd_w3;
struct
{
__IO uint32_t bypassc : 1; /* [0] */
__IO uint32_t reserved1 : 2; /* [2:1] */
__IO uint32_t csts : 1; /* [3] */
__IO uint32_t reserved2 : 28;/* [31:4] */
} xip_cmd_w3_bit;
};
/**
* @brief qspi reserved register, offset:0x40~4C
*/
__IO uint32_t reserved2[4];
/**
* @brief qspi rev register, offset:0x50
*/
union
{
__IO uint32_t rev;
struct
{
__IO uint32_t rev : 32;/* [31:0] */
} rev_bit;
};
/**
* @brief qspi reserved register, offset:0x54~FC
*/
__IO uint32_t reserved3[43];
/**
* @brief qspi dt register, offset:0x100
*/
union
{
__IO uint8_t dt_u8;
__IO uint16_t dt_u16;
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 32;/* [31:0] */
} dt_bit;
};
} qspi_type;
/**
* @}
*/
#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
#define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
/** @defgroup QSPI_exported_functions
* @{
*/
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
uint8_t qspi_byte_read(qspi_type* qspi_x);
uint16_t qspi_half_word_read(qspi_type* qspi_x);
uint32_t qspi_word_read(qspi_type* qspi_x);
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_scfg.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 system config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_SCFG_H
#define __AT32F435_437_SCFG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup SCFG
* @{
*/
#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
/** @defgroup SCFG_exported_types
* @{
*/
/**
* @brief scfg xmc addres mapping swap type
*/
typedef enum
{
SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */
SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */
} scfg_xmc_swap_type;
/**
* @brief scfg infrared modulation signal source selecting type
*/
typedef enum
{
SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
} scfg_ir_source_type;
/**
* @brief scfg infrared output polarity selecting type
*/
typedef enum
{
SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
} scfg_ir_polarity_type;
/**
* @brief scfg memory address mapping selecting type
*/
typedef enum
{
SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
} scfg_mem_map_type;
/**
* @brief scfg pin source type
*/
typedef enum
{
SCFG_PINS_SOURCE0 = 0x00,
SCFG_PINS_SOURCE1 = 0x01,
SCFG_PINS_SOURCE2 = 0x02,
SCFG_PINS_SOURCE3 = 0x03,
SCFG_PINS_SOURCE4 = 0x04,
SCFG_PINS_SOURCE5 = 0x05,
SCFG_PINS_SOURCE6 = 0x06,
SCFG_PINS_SOURCE7 = 0x07,
SCFG_PINS_SOURCE8 = 0x08,
SCFG_PINS_SOURCE9 = 0x09,
SCFG_PINS_SOURCE10 = 0x0A,
SCFG_PINS_SOURCE11 = 0x0B,
SCFG_PINS_SOURCE12 = 0x0C,
SCFG_PINS_SOURCE13 = 0x0D,
SCFG_PINS_SOURCE14 = 0x0E,
SCFG_PINS_SOURCE15 = 0x0F
} scfg_pins_source_type;
/**
* @brief gpio port source type
*/
typedef enum
{
SCFG_PORT_SOURCE_GPIOA = 0x00,
SCFG_PORT_SOURCE_GPIOB = 0x01,
SCFG_PORT_SOURCE_GPIOC = 0x02,
SCFG_PORT_SOURCE_GPIOD = 0x03,
SCFG_PORT_SOURCE_GPIOE = 0x04,
SCFG_PORT_SOURCE_GPIOF = 0x05,
SCFG_PORT_SOURCE_GPIOG = 0x06,
SCFG_PORT_SOURCE_GPIOH = 0x07
} scfg_port_source_type;
/**
* @brief scfg emac interface selecting type
*/
typedef enum
{
SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
} scfg_emac_interface_type;
/**
* @brief scfg ultra high sourcing/sinking strength pins type
*/
typedef enum
{
SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
} scfg_ultra_driven_pins_type;
/**
* @brief type define system config register all
*/
typedef struct
{
/**
* @brief scfg cfg1 register, offset:0x00
*/
union
{
__IO uint32_t cfg1;
struct
{
__IO uint32_t mem_map_sel : 3; /* [2:0] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t ir_pol : 1; /* [5] */
__IO uint32_t ir_src_sel : 2; /* [7:6] */
__IO uint32_t reserved2 : 2; /* [9:8] */
__IO uint32_t swap_xmc : 2; /* [11:10] */
__IO uint32_t reserved3 : 20;/* [31:12] */
} cfg1_bit;
};
/**
* @brief scfg cfg2 register, offset:0x04
*/
union
{
__IO uint32_t cfg2;
struct
{
__IO uint32_t reserved1 : 23;/* [22:0] */
__IO uint32_t mii_rmii_sel : 1; /* [23] */
__IO uint32_t reserved2 : 8; /* [31:24] */
} cfg2_bit;
};
/**
* @brief scfg exintc1 register, offset:0x08
*/
union
{
__IO uint32_t exintc1;
struct
{
__IO uint32_t exint0 : 4; /* [3:0] */
__IO uint32_t exint1 : 4; /* [7:4] */
__IO uint32_t exint2 : 4; /* [11:8] */
__IO uint32_t exint3 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc1_bit;
};
/**
* @brief scfg exintc2 register, offset:0x0C
*/
union
{
__IO uint32_t exintc2;
struct
{
__IO uint32_t exint4 : 4; /* [3:0] */
__IO uint32_t exint5 : 4; /* [7:4] */
__IO uint32_t exint6 : 4; /* [11:8] */
__IO uint32_t exint7 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc2_bit;
};
/**
* @brief scfg exintc3 register, offset:0x10
*/
union
{
__IO uint32_t exintc3;
struct
{
__IO uint32_t exint8 : 4; /* [3:0] */
__IO uint32_t exint9 : 4; /* [7:4] */
__IO uint32_t exint10 : 4; /* [11:8] */
__IO uint32_t exint11 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc3_bit;
};
/**
* @brief scfg exintc4 register, offset:0x14
*/
union
{
__IO uint32_t exintc4;
struct
{
__IO uint32_t exint12 : 4; /* [3:0] */
__IO uint32_t exint13 : 4; /* [7:4] */
__IO uint32_t exint14 : 4; /* [11:8] */
__IO uint32_t exint15 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc4_bit;
};
/**
* @brief crm reserved1 register, offset:0x18~0x28
*/
__IO uint32_t reserved1[5];
/**
* @brief scfg uhdrv register, offset:0x2C
*/
union
{
__IO uint32_t uhdrv;
struct
{
__IO uint32_t pb3_uh : 1; /* [0] */
__IO uint32_t pb9_uh : 1; /* [1] */
__IO uint32_t pb10_uh : 1; /* [2] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t pd12_uh : 1; /* [5] */
__IO uint32_t pd13_uh : 1; /* [6] */
__IO uint32_t pd14_uh : 1; /* [7] */
__IO uint32_t pd15_uh : 1; /* [8] */
__IO uint32_t pf14_uh : 1; /* [9] */
__IO uint32_t pf15_uh : 1; /* [10] */
__IO uint32_t reserved2 : 21;/* [31:11] */
} uhdrv_bit;
};
} scfg_type;
/**
* @}
*/
#define SCFG ((scfg_type *) SCFG_BASE)
/** @defgroup SCFG_exported_functions
* @{
*/
void scfg_reset(void);
void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
void scfg_mem_map_set(scfg_mem_map_type mem_map);
void scfg_emac_interface_set(scfg_emac_interface_type mode);
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_sdio.h Normal file
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@ -0,0 +1,624 @@
/**
**************************************************************************
* @file at32f435_437_sdio.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 sdio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_SDIO_H
#define __AT32F435_437_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_interrupts_definition
* @brief sdio interrupt
* @{
*/
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
/**
* @}
*/
/** @defgroup SDIO_flags_definition
* @brief sdio flag
* @{
*/
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
/**
* @}
*/
/** @defgroup SDIO_exported_types
* @{
*/
/**
* @brief sdio power state
*/
typedef enum
{
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
} sdio_power_state_type;
/**
* @brief sdio edge phase
*/
typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
} sdio_edge_phase_type;
/**
* @brief sdio bus width
*/
typedef enum
{
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
} sdio_bus_width_type;
/**
* @brief sdio response type
*/
typedef enum
{
SDIO_RESPONSE_NO = 0x00, /*!< no response */
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
} sdio_reponse_type;
/**
* @brief sdio wait type
*/
typedef enum
{
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
} sdio_wait_type;
/**
* @brief sdio response register index
*/
typedef enum
{
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
} sdio_rsp_index_type;
/**
* @brief sdio data block size
*/
typedef enum
{
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
} sdio_block_size_type;
/**
* @brief sdio data transfer mode
*/
typedef enum
{
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
} sdio_transfer_mode_type;
/**
* @brief sdio data transfer direction
*/
typedef enum
{
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
} sdio_transfer_direction_type;
/**
* @brief sdio read wait mode
*/
typedef enum
{
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
} sdio_read_wait_mode_type;
/**
* @brief sdio command structure
*/
typedef struct
{
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
uint8_t cmd_index; /*!< the sdio command index */
sdio_reponse_type rsp_type; /*!< the sdio response type */
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
} sdio_command_struct_type;
/**
* @brief sdio data structure
*/
typedef struct
{
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
uint32_t data_length; /*!< the sdio data length */
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
} sdio_data_struct_type;
/**
* @brief type define sdio register all
*/
typedef struct
{
/**
* @brief sdio pwrctrl register, offset:0x00
*/
union
{
__IO uint32_t pwrctrl;
struct
{
__IO uint32_t ps : 2; /* [1:0] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} pwrctrl_bit;
};
/**
* @brief sdio clkctrl register, offset:0x04
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t clkdiv_l : 8; /* [7:0] */
__IO uint32_t clkoen : 1; /* [8] */
__IO uint32_t pwrsven : 1; /* [9] */
__IO uint32_t bypsen : 1; /* [10] */
__IO uint32_t busws : 2; /* [12:11] */
__IO uint32_t clkegs : 1; /* [13] */
__IO uint32_t hfcen : 1; /* [14] */
__IO uint32_t clkdiv_h : 2; /* [16:15] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} clkctrl_bit;
};
/**
* @brief sdio argu register, offset:0x08
*/
union
{
__IO uint32_t argu;
struct
{
__IO uint32_t argu : 32;/* [31:0] */
} argu_bit;
};
/**
* @brief sdio cmdctrl register, offset:0x0C
*/
union
{
__IO uint32_t cmdctrl;
struct
{
__IO uint32_t cmdidx : 6; /* [5:0] */
__IO uint32_t rspwt : 2; /* [7:6] */
__IO uint32_t intwt : 1; /* [8] */
__IO uint32_t pndwt : 1; /* [9] */
__IO uint32_t ccsmen : 1; /* [10] */
__IO uint32_t iosusp : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} cmdctrl_bit;
};
/**
* @brief sdio rspcmd register, offset:0x10
*/
union
{
__IO uint32_t rspcmd;
struct
{
__IO uint32_t rspcmd : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} rspcmd_bit;
};
/**
* @brief sdio rsp1 register, offset:0x14
*/
union
{
__IO uint32_t rsp1;
struct
{
__IO uint32_t cardsts1 : 32;/* [31:0] */
} rsp1_bit;
};
/**
* @brief sdio rsp2 register, offset:0x18
*/
union
{
__IO uint32_t rsp2;
struct
{
__IO uint32_t cardsts2 : 32;/* [31:0] */
} rsp2_bit;
};
/**
* @brief sdio rsp3 register, offset:0x1C
*/
union
{
__IO uint32_t rsp3;
struct
{
__IO uint32_t cardsts3 : 32;/* [31:0] */
} rsp3_bit;
};
/**
* @brief sdio rsp4 register, offset:0x20
*/
union
{
__IO uint32_t rsp4;
struct
{
__IO uint32_t cardsts4 : 32;/* [31:0] */
} rsp4_bit;
};
/**
* @brief sdio dttmr register, offset:0x24
*/
union
{
__IO uint32_t dttmr;
struct
{
__IO uint32_t timeout : 32;/* [31:0] */
} dttmr_bit;
};
/**
* @brief sdio dtlen register, offset:0x28
*/
union
{
__IO uint32_t dtlen;
struct
{
__IO uint32_t dtlen : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtlen_bit;
};
/**
* @brief sdio dtctrl register, offset:0x2C
*/
union
{
__IO uint32_t dtctrl;
struct
{
__IO uint32_t tfren : 1; /* [0] */
__IO uint32_t tfrdir : 1; /* [1] */
__IO uint32_t tfrmode : 1; /* [2] */
__IO uint32_t dmaen : 1; /* [3] */
__IO uint32_t blksize : 4; /* [7:4] */
__IO uint32_t rdwtstart : 1; /* [8] */
__IO uint32_t rdwtstop : 1; /* [9] */
__IO uint32_t rdwtmode : 1; /* [10] */
__IO uint32_t ioen : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} dtctrl_bit;
};
/**
* @brief sdio dtcnt register, offset:0x30
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtcnt_bit;
};
/**
* @brief sdio sts register, offset:0x34
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t docmd : 1; /* [11] */
__IO uint32_t dotx : 1; /* [12] */
__IO uint32_t dorx : 1; /* [13] */
__IO uint32_t txbufh : 1; /* [14] */
__IO uint32_t rxbufh : 1; /* [15] */
__IO uint32_t txbuff : 1; /* [16] */
__IO uint32_t rxbuff : 1; /* [17] */
__IO uint32_t txbufe : 1; /* [18] */
__IO uint32_t rxbufe : 1; /* [19] */
__IO uint32_t txbuf : 1; /* [20] */
__IO uint32_t rxbuf : 1; /* [21] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} sts_bit;
};
/**
* @brief sdio intclr register, offset:0x38
*/
union
{
__IO uint32_t intclr;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t reserved1 : 11;/* [21:11] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved2 : 9; /* [31:23] */
} intclr_bit;
};
/**
* @brief sdio inten register, offset:0x3C
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t cmdfailien : 1; /* [0] */
__IO uint32_t dtfailien : 1; /* [1] */
__IO uint32_t cmdtimeoutien : 1; /* [2] */
__IO uint32_t dttimeoutien : 1; /* [3] */
__IO uint32_t txerruien : 1; /* [4] */
__IO uint32_t rxerroien : 1; /* [5] */
__IO uint32_t cmdrspcmplien : 1; /* [6] */
__IO uint32_t cmdcmplien : 1; /* [7] */
__IO uint32_t dtcmplien : 1; /* [8] */
__IO uint32_t sbiterrien : 1; /* [9] */
__IO uint32_t dtblkcmplien : 1; /* [10] */
__IO uint32_t docmdien : 1; /* [11] */
__IO uint32_t dotxien : 1; /* [12] */
__IO uint32_t dorxien : 1; /* [13] */
__IO uint32_t txbufhien : 1; /* [14] */
__IO uint32_t rxbufhien : 1; /* [15] */
__IO uint32_t txbuffien : 1; /* [16] */
__IO uint32_t rxbuffien : 1; /* [17] */
__IO uint32_t txbufeien : 1; /* [18] */
__IO uint32_t rxbufeien : 1; /* [19] */
__IO uint32_t txbufien : 1; /* [20] */
__IO uint32_t rxbufien : 1; /* [21] */
__IO uint32_t ioifien : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} inten_bit;
};
/**
* @brief sdio reserved1 register, offset:0x40~0x44
*/
__IO uint32_t reserved1[2];
/**
* @brief sdio bufcnt register, offset:0x48
*/
union
{
__IO uint32_t bufcnt;
struct
{
__IO uint32_t cnt : 24;/* [23:0] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} bufcnt_bit;
};
/**
* @brief sdio reserved2 register, offset:0x4C~0x7C
*/
__IO uint32_t reserved2[13];
/**
* @brief sdio buf register, offset:0x80
*/
union
{
__IO uint32_t buf;
struct
{
__IO uint32_t dt : 32;/* [31:0] */
} buf_bit;
};
} sdio_type;
/**
* @}
*/
#define SDIO1 ((sdio_type *) SDIO1_BASE)
#define SDIO2 ((sdio_type *) SDIO2_BASE)
/** @defgroup SDIO_exported_functions
* @{
*/
void sdio_reset(sdio_type *sdio_x);
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint8_t sdio_command_response_get(sdio_type *sdio_x);
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
uint32_t sdio_data_read(sdio_type *sdio_x);
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_spi.h Normal file
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@ -0,0 +1,505 @@
/**
**************************************************************************
* @file at32f435_437_spi.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 spi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_SPI_H
#define __AT32F435_437_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/**
* @defgroup SPI_I2S_flags_definition
* @brief spi i2s flag
* @{
*/
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
#define SPI_CSPAS_FLAG 0x0100 /*!< spi cs pulse abnormal setting fiag */
/**
* @}
*/
/**
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
*/
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
/**
* @}
*/
/** @defgroup SPI_exported_types
* @{
*/
/**
* @brief spi frame bit num type
*/
typedef enum
{
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
} spi_frame_bit_num_type;
/**
* @brief spi master/slave mode type
*/
typedef enum
{
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
} spi_master_slave_mode_type;
/**
* @brief spi clock polarity (clkpol) type
*/
typedef enum
{
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
} spi_clock_polarity_type;
/**
* @brief spi clock phase (clkpha) type
*/
typedef enum
{
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
} spi_clock_phase_type;
/**
* @brief spi cs mode type
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**
* @brief spi master clock frequency division type
*/
typedef enum
{
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
} spi_mclk_freq_div_type;
/**
* @brief spi transmit first bit (lsb/msb) type
*/
typedef enum
{
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
} spi_first_bit_type;
/**
* @brief spi transmission mode type
*/
typedef enum
{
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
} spi_transmission_mode_type;
/**
* @brief spi crc direction type
*/
typedef enum
{
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
} spi_crc_direction_type;
/**
* @brief spi single line bidirectional direction type
*/
typedef enum
{
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
} spi_half_duplex_direction_type;
/**
* @brief spi software cs internal level type
*/
typedef enum
{
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
} spi_software_cs_level_type;
/**
* @brief i2s audio protocol type
*/
typedef enum
{
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
} i2s_audio_protocol_type;
/**
* @brief i2s audio frequency type
*/
typedef enum
{
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
} i2s_audio_sampling_freq_type;
/**
* @brief i2s data bit num and channel bit num type
*/
typedef enum
{
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
} i2s_data_channel_format_type;
/**
* @brief i2s operation mode type
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
} i2s_operation_mode_type;
/**
* @brief i2s clock polarity type
*/
typedef enum
{
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
} i2s_clock_polarity_type;
/**
* @brief spi init type
*/
typedef struct
{
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_phase_type clock_phase; /*!< clock phase selection */
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
} spi_init_type;
/**
* @brief i2s init type
*/
typedef struct
{
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
confirm_state mclk_output_enable; /*!< mclk_output selection */
} i2s_init_type;
/**
* @brief type define spi register all
*/
typedef struct
{
/**
* @brief spi ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t clkpha : 1; /* [0] */
__IO uint32_t clkpol : 1; /* [1] */
__IO uint32_t msten : 1; /* [2] */
__IO uint32_t mdiv_l : 3; /* [5:3] */
__IO uint32_t spien : 1; /* [6] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t swcsil : 1; /* [8] */
__IO uint32_t swcsen : 1; /* [9] */
__IO uint32_t ora : 1; /* [10] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t ntc : 1; /* [12] */
__IO uint32_t ccen : 1; /* [13] */
__IO uint32_t slbtd : 1; /* [14] */
__IO uint32_t slben : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief spi ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t dmaren : 1; /* [0] */
__IO uint32_t dmaten : 1; /* [1] */
__IO uint32_t hwcsoe : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t tien : 1; /* [4] */
__IO uint32_t errie : 1; /* [5] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t tdbeie : 1; /* [7] */
__IO uint32_t mdiv_h : 1; /* [8] */
__IO uint32_t mdiv3en : 1; /* [9] */
__IO uint32_t reserved2 : 22;/* [31:10] */
} ctrl2_bit;
};
/**
* @brief spi sts register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rdbf : 1; /* [0] */
__IO uint32_t tdbe : 1; /* [1] */
__IO uint32_t acs : 1; /* [2] */
__IO uint32_t tuerr : 1; /* [3] */
__IO uint32_t ccerr : 1; /* [4] */
__IO uint32_t mmerr : 1; /* [5] */
__IO uint32_t roerr : 1; /* [6] */
__IO uint32_t bf : 1; /* [7] */
__IO uint32_t cspas : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} sts_bit;
};
/**
* @brief spi dt register, offset:0x0C
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dt_bit;
};
/**
* @brief spi cpoly register, offset:0x10
*/
union
{
__IO uint32_t cpoly;
struct
{
__IO uint32_t cpoly : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cpoly_bit;
};
/**
* @brief spi rcrc register, offset:0x14
*/
union
{
__IO uint32_t rcrc;
struct
{
__IO uint32_t rcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} rcrc_bit;
};
/**
* @brief spi tcrc register, offset:0x18
*/
union
{
__IO uint32_t tcrc;
struct
{
__IO uint32_t tcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} tcrc_bit;
};
/**
* @brief spi i2sctrl register, offset:0x1C
*/
union
{
__IO uint32_t i2sctrl;
struct
{
__IO uint32_t i2scbn : 1; /* [0] */
__IO uint32_t i2sdbn : 2; /* [2:1] */
__IO uint32_t i2sclkpol : 1; /* [3] */
__IO uint32_t stdsel : 2; /* [5:4] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t pcmfssel : 1; /* [7] */
__IO uint32_t opersel : 2; /* [9:8] */
__IO uint32_t i2sen : 1; /* [10] */
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
};
/**
* @brief spi i2sclk register, offset:0x20
*/
union
{
__IO uint32_t i2sclk;
struct
{
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
__IO uint32_t i2sodd : 1; /* [8] */
__IO uint32_t i2smclkoe : 1; /* [9] */
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
};
} spi_type;
/**
* @}
*/
#define SPI1 ((spi_type *) SPI1_BASE)
#define SPI2 ((spi_type *) SPI2_BASE)
#define SPI3 ((spi_type *) SPI3_BASE)
#define SPI4 ((spi_type *) SPI4_BASE)
#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
/** @defgroup SPI_exported_functions
* @{
*/
void spi_i2s_reset(spi_type *spi_x);
void spi_default_para_init(spi_init_type* spi_init_struct);
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
void spi_crc_next_transmit(spi_type* spi_x);
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
void spi_enable(spi_type* spi_x, confirm_state new_state);
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
void i2s_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_usart.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 usart header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_USART_H
#define __AT32F435_437_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_flags_definition
* @brief usart flag
* @{
*/
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
/**
* @}
*/
/** @defgroup USART_interrupts_definition
* @brief usart interrupt
* @{
*/
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
/**
* @}
*/
/** @defgroup USART_exported_types
* @{
*/
/**
* @brief usart parity selection type
*/
typedef enum
{
USART_PARITY_NONE = 0x00, /*!< usart no parity */
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
} usart_parity_selection_type;
/**
* @brief usart wakeup mode type
*/
typedef enum
{
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
} usart_wakeup_mode_type;
/**
* @brief usart data bit num type
*/
typedef enum
{
USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
} usart_data_bit_num_type;
/**
* @brief usart break frame bit num type
*/
typedef enum
{
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
} usart_break_bit_num_type;
/**
* @brief usart phase of the clock type
*/
typedef enum
{
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
} usart_clock_phase_type;
/**
* @brief usart polarity of the clock type
*/
typedef enum
{
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
} usart_clock_polarity_type;
/**
* @brief usart last bit clock pulse type
*/
typedef enum
{
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
} usart_lbcp_type;
/**
* @brief usart stop bit num type
*/
typedef enum
{
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
} usart_stop_bit_num_type;
/**
* @brief usart hardware flow control type
*/
typedef enum
{
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
} usart_hardware_flow_control_type;
/**
* @brief usart identification bit num type
*/
typedef enum
{
USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
} usart_identification_bit_num_type;
/**
* @brief usart de polarity type
*/
typedef enum
{
USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
} usart_de_polarity_type;
/**
* @brief type define usart register all
*/
typedef struct
{
/**
* @brief usart sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t perr : 1; /* [0] */
__IO uint32_t ferr : 1; /* [1] */
__IO uint32_t nerr : 1; /* [2] */
__IO uint32_t roerr : 1; /* [3] */
__IO uint32_t idlef : 1; /* [4] */
__IO uint32_t rdbf : 1; /* [5] */
__IO uint32_t tdc : 1; /* [6] */
__IO uint32_t tdbe : 1; /* [7] */
__IO uint32_t bff : 1; /* [8] */
__IO uint32_t ctscf : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} sts_bit;
};
/**
* @brief usart dt register, offset:0x04
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 9; /* [8:0] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} dt_bit;
};
/**
* @brief usart baudr register, offset:0x08
*/
union
{
__IO uint32_t baudr;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} baudr_bit;
};
/**
* @brief usart ctrl1 register, offset:0x0C
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t sbf : 1; /* [0] */
__IO uint32_t rm : 1; /* [1] */
__IO uint32_t ren : 1; /* [2] */
__IO uint32_t ten : 1; /* [3] */
__IO uint32_t idleien : 1; /* [4] */
__IO uint32_t rdbfien : 1; /* [5] */
__IO uint32_t tdcien : 1; /* [6] */
__IO uint32_t tdbeien : 1; /* [7] */
__IO uint32_t perrien : 1; /* [8] */
__IO uint32_t psel : 1; /* [9] */
__IO uint32_t pen : 1; /* [10] */
__IO uint32_t wum : 1; /* [11] */
__IO uint32_t dbn_l : 1; /* [12] */
__IO uint32_t uen : 1; /* [13] */
__IO uint32_t reserved1 : 2; /* [15:14] */
__IO uint32_t tcdt : 5; /* [20:16] */
__IO uint32_t tsdt : 5; /* [25:21] */
__IO uint32_t reserved2 : 2; /* [27:26] */
__IO uint32_t dbn_h : 1; /* [28] */
__IO uint32_t reserved3 : 3; /* [31:29] */
} ctrl1_bit;
};
/**
* @brief usart ctrl2 register, offset:0x10
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t id_l : 4; /* [3:0] */
__IO uint32_t idbn : 1; /* [4] */
__IO uint32_t bfbn : 1; /* [5] */
__IO uint32_t bfien : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t lbcp : 1; /* [8] */
__IO uint32_t clkpha : 1; /* [9] */
__IO uint32_t clkpol : 1; /* [10] */
__IO uint32_t clken : 1; /* [11] */
__IO uint32_t stopbn : 2; /* [13:12] */
__IO uint32_t linen : 1; /* [14] */
__IO uint32_t trpswap : 1; /* [15] */
__IO uint32_t reserved2 : 12;/* [27:16] */
__IO uint32_t id_h : 4; /* [31:28] */
} ctrl2_bit;
};
/**
* @brief usart ctrl3 register, offset:0x14
*/
union
{
__IO uint32_t ctrl3;
struct
{
__IO uint32_t errien : 1; /* [0] */
__IO uint32_t irdaen : 1; /* [1] */
__IO uint32_t irdalp : 1; /* [2] */
__IO uint32_t slben : 1; /* [3] */
__IO uint32_t scnacken : 1; /* [4] */
__IO uint32_t scmen : 1; /* [5] */
__IO uint32_t dmaren : 1; /* [6] */
__IO uint32_t dmaten : 1; /* [7] */
__IO uint32_t rtsen : 1; /* [8] */
__IO uint32_t ctsen : 1; /* [9] */
__IO uint32_t ctscfien : 1; /* [10] */
__IO uint32_t reserved1 : 3; /* [13:11] */
__IO uint32_t rs485en : 1; /* [14] */
__IO uint32_t dep : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} ctrl3_bit;
};
/**
* @brief usart gdiv register, offset:0x18
*/
union
{
__IO uint32_t gdiv;
struct
{
__IO uint32_t isdiv : 8; /* [7:0] */
__IO uint32_t scgt : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} gdiv_bit;
};
} usart_type;
/**
* @}
*/
#define USART1 ((usart_type *) USART1_BASE)
#define USART2 ((usart_type *) USART2_BASE)
#define USART3 ((usart_type *) USART3_BASE)
#define UART4 ((usart_type *) UART4_BASE)
#define UART5 ((usart_type *) UART5_BASE)
#define USART6 ((usart_type *) USART6_BASE)
#define UART7 ((usart_type *) UART7_BASE)
#define UART8 ((usart_type *) UART8_BASE)
/** @defgroup USART_exported_functions
* @{
*/
void usart_reset(usart_type* usart_x);
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
void usart_enable(usart_type* usart_x, confirm_state new_state);
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_data_transmit(usart_type* usart_x, uint16_t data);
uint16_t usart_data_receive(usart_type* usart_x);
void usart_break_send(usart_type* usart_x);
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_wdt.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 wdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_WDT_H
#define __AT32F435_437_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup WDT
* @{
*/
/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
/**
* @}
*/
/** @defgroup WDT_exported_types
* @{
*/
/**
* @brief wdt division value type
*/
typedef enum
{
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
} wdt_cmd_value_type;
/**
* @brief type define wdt register all
*/
typedef struct
{
/**
* @brief wdt cmd register, offset:0x00
*/
union
{
__IO uint32_t cmd;
struct
{
__IO uint32_t cmd : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cmd_bit;
};
/**
* @brief wdt div register, offset:0x04
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 3; /* [2:0] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} div_bit;
};
/**
* @brief wdt rld register, offset:0x08
*/
union
{
__IO uint32_t rld;
struct
{
__IO uint32_t rld : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} rld_bit;
};
/**
* @brief wdt sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t divf : 1; /* [0] */
__IO uint32_t rldf : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
/**
* @brief wdt win register, offset:0x10
*/
union
{
__IO uint32_t win;
struct
{
__IO uint32_t win : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} win_bit;
};
} wdt_type;
/**
* @}
*/
#define WDT ((wdt_type *) WDT_BASE)
/** @defgroup WDT_exported_functions
* @{
*/
void wdt_enable(void);
void wdt_counter_reload(void);
void wdt_reload_value_set(uint16_t reload_value);
void wdt_divider_set(wdt_division_type division);
void wdt_register_write_enable( confirm_state new_state);
flag_status wdt_flag_get(uint16_t wdt_flag);
void wdt_window_counter_set(uint16_t window_cnt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_wwdt.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_WWDT_H
#define __AT32F435_437_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @addtogroup WWDT
* @{
*/
/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
* @}
*/
/** @defgroup WWDT_exported_types
* @{
*/
/**
* @brief wwdt division type
*/
typedef enum
{
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
} wwdt_division_type;
/**
* @brief type define wwdt register all
*/
typedef struct
{
/**
* @brief wwdt ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t cnt : 7; /* [6:0] */
__IO uint32_t wwdten : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} ctrl_bit;
};
/**
* @brief wwdt cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t win : 7; /* [6:0] */
__IO uint32_t div : 2; /* [8:7] */
__IO uint32_t rldien : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} cfg_bit;
};
/**
* @brief wwdt cfg register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rldf : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} sts_bit;
};
} wwdt_type;
/**
* @}
*/
#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{
*/
void wwdt_reset(void);
void wwdt_divider_set(wwdt_division_type division);
void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_acc.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup ACC
* @brief ACC driver modules
* @{
*/
#ifdef ACC_MODULE_ENABLED
/** @defgroup ACC_private_functions
* @{
*/
/**
* @brief enable or disable the acc calibration mode.
* @param acc_trim: specifies the acc calibration type.
* this parameter can be one of the following values:
* - ACC_CAL_HICKCAL
* - ACC_CAL_HICKTRIM
* @param new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
* @retval none
*/
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
{
if(acc_trim == ACC_CAL_HICKCAL)
{
ACC->ctrl1_bit.entrim = FALSE;
}
else
{
ACC->ctrl1_bit.entrim = TRUE;
}
ACC->ctrl1_bit.calon = new_state;
}
/**
* @brief store calibration step data in acc's ctrl1 register.
* @param step_value: value to be stored in the acc's ctrl1 register
* @retval none
*/
void acc_step_set(uint8_t step_value)
{
ACC->ctrl1_bit.step = step_value;
}
/**
* @brief select sof sourse for acc in acc's ctrl1 register.
* @param sof_sel: value to be stored in the acc's ctrl1 register
* this parameter can be one of the following values:
* @arg ACC_SOF_OTG1
* @arg ACC_SOF_OTG2
* @retval none
*/
void acc_sof_select(uint16_t sof_sel)
{
ACC->ctrl1 |= sof_sel;
}
/**
* @brief enable or disable the specified acc interrupts.
* @param acc_int: specifies the acc interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - ACC_CALRDYIEN_INT
* - ACC_EIEN_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
{
if(acc_int == ACC_CALRDYIEN_INT)
{
ACC->ctrl1_bit.calrdyien = new_state;
}
else
{
ACC->ctrl1_bit.eien = new_state;
}
}
/**
* @brief return the current acc hicktrim value.
* @param none
* @retval 8-bit hicktrim value.
*/
uint8_t acc_hicktrim_get(void)
{
return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
}
/**
* @brief return the current acc hickcal value.
* @param none
* @retval 8-bit hicktrim value.
*/
uint8_t acc_hickcal_get(void)
{
return ((uint8_t)(ACC->ctrl2_bit.hickcal));
}
/**
* @brief wtire the value to acc c1 register.
* @param acc_c1_value
* @retval none.
*/
void acc_write_c1(uint16_t acc_c1_value)
{
ACC->c1 = acc_c1_value;
}
/**
* @brief wtire the value to acc c2 register.
* @param acc_c2_value
* @retval none.
*/
void acc_write_c2(uint16_t acc_c2_value)
{
ACC->c2 = acc_c2_value;
}
/**
* @brief wtire the value to acc c3 register.
* @param acc_c3_value
* @retval none.
*/
void acc_write_c3(uint16_t acc_c3_value)
{
ACC->c3 = acc_c3_value;
}
/**
* @brief return the current acc c1 value.
* @param none
* @retval 16-bit c1 value.
*/
uint16_t acc_read_c1(void)
{
return ((uint16_t)(ACC->c1));
}
/**
* @brief return the current acc c2 value.
* @param none
* @retval 16-bit c2 value.
*/
uint16_t acc_read_c2(void)
{
return ((uint16_t)(ACC->c2));
}
/**
* @brief return the current acc c3 value.
* @param none
* @retval 16-bit c3 value.
*/
uint16_t acc_read_c3(void)
{
return ((uint16_t)(ACC->c3));
}
/**
* @brief check whether the specified acc flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be one of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status acc_flag_get(uint16_t acc_flag)
{
if(acc_flag == ACC_CALRDY_FLAG)
return (flag_status)(ACC->sts_bit.calrdy);
else
return (flag_status)(ACC->sts_bit.rslost);
}
/**
* @brief clear the specified acc flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval none
*/
void acc_flag_clear(uint16_t acc_flag)
{
ACC->sts = ~acc_flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_crc.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
#ifdef CRC_MODULE_ENABLED
/** @defgroup CRC_private_functions
* @{
*/
/**
* @brief reset the crc data register.
* @param none
* @retval none
*/
void crc_data_reset(void)
{
/* reset crc generator */
CRC->ctrl_bit.rst = 0x1;
}
/**
* @brief compute the 32-bit crc of a given data word(32-bit).
* @param data: data word(32-bit) to compute its crc
* @retval 32-bit crc
*/
uint32_t crc_one_word_calculate(uint32_t data)
{
CRC->dt = data;
return (CRC->dt);
}
/**
* @brief compute the 32-bit crc of a given buffer of data word(32-bit).
* @param pbuffer: pointer to the buffer containing the data to be computed
* @param length: length of the buffer to be computed
* @retval 32-bit crc
*/
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
{
uint32_t index = 0;
for(index = 0; index < length; index++)
{
CRC->dt = pbuffer[index];
}
return (CRC->dt);
}
/**
* @brief return the current crc value.
* @param none
* @retval 32-bit crc
*/
uint32_t crc_data_get(void)
{
return (CRC->dt);
}
/**
* @brief store a 8-bit data in the common data register.
* @param cdt_value: 8-bit value to be stored in the common data register
* @retval none
*/
void crc_common_data_set(uint8_t cdt_value)
{
CRC->cdt_bit.cdt = cdt_value;
}
/**
* @brief return the 8-bit data stored in the common data register
* @param none
* @retval 8-bit value of the common data register
*/
uint8_t crc_common_data_get(void)
{
return (CRC->cdt_bit.cdt);
}
/**
* @brief set the 32-bit initial data of crc
* @param value: initial data
* @retval none
*/
void crc_init_data_set(uint32_t value)
{
CRC->idt = value;
}
/**
* @brief control the reversal of the bit order in the input data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_INPUT_NO_AFFECTE
* - CRC_REVERSE_INPUT_BY_BYTE
* - CRC_REVERSE_INPUT_BY_HALFWORD
* - CRC_REVERSE_INPUT_BY_WORD
* @retval none.
*/
void crc_reverse_input_data_set(crc_reverse_input_type value)
{
CRC->ctrl_bit.revid = value;
}
/**
* @brief control the reversal of the bit order in the output data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_OUTPUT_NO_AFFECTE
* - CRC_REVERSE_OUTPUT_DATA
* @retval none.
*/
void crc_reverse_output_data_set(crc_reverse_output_type value)
{
CRC->ctrl_bit.revod = value;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_crm.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup CRM
* @brief CRM driver modules
* @{
*/
#ifdef CRM_MODULE_ENABLED
/** @defgroup CRM_private_functions
* @{
*/
/**
* @brief reset the crm register
* @param none
* @retval none
*/
void crm_reset(void)
{
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = TRUE;
/* wait hick stable */
while(CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset pllms pllns pllfr pllrcs bits */
CRM->pllcfg = 0x00033002U;
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000U;
}
/**
* @brief enable or disable crm low speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_lext_bypass(confirm_state new_state)
{
CRM->bpdc_bit.lextbyps = new_state;
}
/**
* @brief enable or disable crm high speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_hext_bypass(confirm_state new_state)
{
CRM->ctrl_bit.hextbyps = new_state;
}
/**
* @brief get crm flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_HICK_STABLE_FLAG
* - CRM_HEXT_STABLE_FLAG
* - CRM_PLL_STABLE_FLAG
* - CRM_LEXT_STABLE_FLAG
* - CRM_LICK_STABLE_FLAG
* - CRM_PIN_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_flag_get(uint32_t flag)
{
flag_status status = RESET;
if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief wait for hext stable
* @param none
* @retval error_status (ERROR or SUCCESS)
*/
error_status crm_hext_stable_wait(void)
{
uint32_t stable_cnt = 0;
error_status status = ERROR;
while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
{
stable_cnt ++;
}
if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
return status;
}
/**
* @brief set the hick trimming value
* @param trim_value (0x00~0x3F)
* @retval none
*/
void crm_hick_clock_trimming_set(uint8_t trim_value)
{
CRM->ctrl_bit.hicktrim = trim_value;
}
/**
* @brief set the crm calibration value
* @param cali_value (0x00~0xFF)
* @retval none
*/
void crm_hick_clock_calibration_set(uint8_t cali_value)
{
/* enable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x5A;
/* write hick calibration value */
CRM->ctrl_bit.hickcal = cali_value;
/* disable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x0;
}
/**
* @brief enable or disable the peripheral clock
* @param value
* this parameter can be one of the following values:
* - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK - CRM_GPIOC_PERIPH_CLOCK - CRM_GPIOD_PERIPH_CLOCK
* - CRM_GPIOE_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_GPIOG_PERIPH_CLOCK - CRM_GPIOH_PERIPH_CLOCK
* - CRM_CRC_PERIPH_CLOCK - CRM_EDMA_PERIPH_CLOCK - CRM_DMA1_PERIPH_CLOCK - CRM_DMA2_PERIPH_CLOCK
* - CRM_EMAC_PERIPH_CLOCK - CRM_EMACTX_PERIPH_CLOCK - CRM_EMACRX_PERIPH_CLOCK - CRM_EMACPTP_PERIPH_CLOCK
* - CRM_OTGFS2_PERIPH_CLOCK - CRM_DVP_PERIPH_CLOCK - CRM_OTGFS1_PERIPH_CLOCK - CRM_SDIO1_PERIPH_CLOCK
* - CRM_XMC_PERIPH_CLOCK - CRM_QSPI1_PERIPH_CLOCK - CRM_QSPI2_PERIPH_CLOCK - CRM_SDIO2_PERIPH_CLOCK
* - CRM_TMR2_PERIPH_CLOCK - CRM_TMR3_PERIPH_CLOCK - CRM_TMR4_PERIPH_CLOCK - CRM_TMR5_PERIPH_CLOCK
* - CRM_TMR6_PERIPH_CLOCK - CRM_TMR7_PERIPH_CLOCK - CRM_TMR12_PERIPH_CLOCK - CRM_TMR13_PERIPH_CLOCK
* - CRM_TMR14_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK - CRM_SPI2_PERIPH_CLOCK - CRM_SPI3_PERIPH_CLOCK
* - CRM_USART2_PERIPH_CLOCK - CRM_USART3_PERIPH_CLOCK - CRM_UART4_PERIPH_CLOCK - CRM_UART5_PERIPH_CLOCK
* - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_I2C3_PERIPH_CLOCK - CRM_CAN1_PERIPH_CLOCK
* - CRM_CAN2_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK - CRM_DAC_PERIPH_CLOCK - CRM_UART7_PERIPH_CLOCK
* - CRM_UART8_PERIPH_CLOCK - CRM_TMR1_PERIPH_CLOCK - CRM_TMR8_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK
* - CRM_USART6_PERIPH_CLOCK - CRM_ADC1_PERIPH_CLOCK - CRM_ADC2_PERIPH_CLOCK - CRM_ADC3_PERIPH_CLOCK
* - CRM_SPI1_PERIPH_CLOCK - CRM_SPI4_PERIPH_CLOCK - CRM_SCFG_PERIPH_CLOCK - CRM_TMR9_PERIPH_CLOCK
* - CRM_TMR10_PERIPH_CLOCK - CRM_TMR11_PERIPH_CLOCK - CRM_TMR20_PERIPH_CLOCK - CRM_ACC_PERIPH_CLOCK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
{
/* enable periph clock */
if(TRUE == new_state)
{
CRM_REG(value) |= CRM_REG_BIT(value);
}
/* disable periph clock */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral reset
* @param value
* this parameter can be one of the following values:
* - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET - CRM_GPIOC_PERIPH_RESET - CRM_GPIOD_PERIPH_RESET
* - CRM_GPIOE_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET - CRM_GPIOG_PERIPH_RESET - CRM_GPIOH_PERIPH_RESET
* - CRM_CRC_PERIPH_RESET - CRM_EDMA_PERIPH_RESET - CRM_DMA1_PERIPH_RESET - CRM_DMA2_PERIPH_RESET
* - CRM_EMAC_PERIPH_RESET - CRM_OTGFS2_PERIPH_RESET - CRM_DVP_PERIPH_RESET - CRM_OTGFS1_PERIPH_RESET
* - CRM_SDIO1_PERIPH_RESET - CRM_XMC_PERIPH_RESET - CRM_QSPI1_PERIPH_RESET - CRM_QSPI2_PERIPH_RESET
* - CRM_SDIO2_PERIPH_RESET - CRM_TMR2_PERIPH_RESET - CRM_TMR3_PERIPH_RESET - CRM_TMR4_PERIPH_RESET
* - CRM_TMR5_PERIPH_RESET - CRM_TMR6_PERIPH_RESET - CRM_TMR7_PERIPH_RESET - CRM_TMR12_PERIPH_RESET
* - CRM_TMR13_PERIPH_RESET - CRM_TMR14_PERIPH_RESET - CRM_WWDT_PERIPH_RESET - CRM_SPI2_PERIPH_RESET
* - CRM_SPI3_PERIPH_RESET - CRM_USART2_PERIPH_RESET - CRM_USART3_PERIPH_RESET - CRM_UART4_PERIPH_RESET
* - CRM_UART5_PERIPH_RESET - CRM_I2C1_PERIPH_RESET - CRM_I2C2_PERIPH_RESET - CRM_I2C3_PERIPH_RESET
* - CRM_CAN1_PERIPH_RESET - CRM_CAN2_PERIPH_RESET - CRM_PWC_PERIPH_RESET - CRM_DAC_PERIPH_RESET
* - CRM_UART7_PERIPH_RESET - CRM_UART8_PERIPH_RESET - CRM_TMR1_PERIPH_RESET - CRM_TMR8_PERIPH_RESET
* - CRM_USART1_PERIPH_RESET - CRM_USART6_PERIPH_RESET - CRM_ADC_PERIPH_RESET - CRM_SPI1_PERIPH_RESET
* - CRM_SPI4_PERIPH_RESET - CRM_SCFG_PERIPH_RESET - CRM_TMR9_PERIPH_RESET - CRM_TMR10_PERIPH_RESET
* - CRM_TMR11_PERIPH_RESET - CRM_TMR20_PERIPH_RESET - CRM_ACC_PERIPH_RESET
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
{
/* enable periph reset */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable periph reset */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral clock in lowpower mode
* @param value
* this parameter can be one of the following values:
* - CRM_GPIOA_PERIPH_LOWPOWER - CRM_GPIOB_PERIPH_LOWPOWER - CRM_GPIOC_PERIPH_LOWPOWER - CRM_GPIOD_PERIPH_LOWPOWER
* - CRM_GPIOE_PERIPH_LOWPOWER - CRM_GPIOF_PERIPH_LOWPOWER - CRM_GPIOG_PERIPH_LOWPOWER - CRM_GPIOH_PERIPH_LOWPOWER
* - CRM_CRC_PERIPH_LOWPOWER - CRM_EDMA_PERIPH_LOWPOWER - CRM_DMA1_PERIPH_LOWPOWER - CRM_DMA2_PERIPH_LOWPOWER
* - CRM_EMAC_PERIPH_LOWPOWER - CRM_EMACTX_PERIPH_LOWPOWER - CRM_EMACRX_PERIPH_LOWPOWER - CRM_EMACPTP_PERIPH_LOWPOWER
* - CRM_OTGFS2_PERIPH_LOWPOWER - CRM_DVP_PERIPH_LOWPOWER - CRM_OTGFS1_PERIPH_LOWPOWER - CRM_SDIO1_PERIPH_LOWPOWER
* - CRM_XMC_PERIPH_LOWPOWER - CRM_QSPI1_PERIPH_LOWPOWER - CRM_QSPI2_PERIPH_LOWPOWER - CRM_SDIO2_PERIPH_LOWPOWER
* - CRM_TMR2_PERIPH_LOWPOWER - CRM_TMR3_PERIPH_LOWPOWER - CRM_TMR4_PERIPH_LOWPOWER - CRM_TMR5_PERIPH_LOWPOWER
* - CRM_TMR6_PERIPH_LOWPOWER - CRM_TMR7_PERIPH_LOWPOWER - CRM_TMR12_PERIPH_LOWPOWER - CRM_TMR13_PERIPH_LOWPOWER
* - CRM_TMR14_PERIPH_LOWPOWER - CRM_WWDT_PERIPH_LOWPOWER - CRM_SPI2_PERIPH_LOWPOWER - CRM_SPI3_PERIPH_LOWPOWER
* - CRM_USART2_PERIPH_LOWPOWER - CRM_USART3_PERIPH_LOWPOWER - CRM_UART4_PERIPH_LOWPOWER - CRM_UART5_PERIPH_LOWPOWER
* - CRM_I2C1_PERIPH_LOWPOWER - CRM_I2C2_PERIPH_LOWPOWER - CRM_I2C3_PERIPH_LOWPOWER - CRM_CAN1_PERIPH_LOWPOWER
* - CRM_CAN2_PERIPH_LOWPOWER - CRM_PWC_PERIPH_LOWPOWER - CRM_DAC_PERIPH_LOWPOWER - CRM_UART7_PERIPH_LOWPOWER
* - CRM_UART8_PERIPH_LOWPOWER - CRM_TMR1_PERIPH_LOWPOWER - CRM_TMR8_PERIPH_LOWPOWER - CRM_USART1_PERIPH_LOWPOWER
* - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC1_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER - CRM_ADC3_PERIPH_LOWPOWER
* - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER - CRM_TMR9_PERIPH_LOWPOWER
* - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_TMR20_PERIPH_LOWPOWER - CRM_ACC_PERIPH_LOWPOWER
* - CRM_FLASH_PERIPH_LOWPOWER - CRM_SRAM1_PERIPH_LOWPOWER - CRM_SRAM2_PERIPH_LOWPOWER
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state)
{
/* enable periph clock in lowpower mode */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable periph clock in lowpower mode */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the crm clock source
* @param source
* this parameter can be one of the following values:
* - CRM_CLOCK_SOURCE_HICK
* - CRM_CLOCK_SOURCE_HEXT
* - CRM_CLOCK_SOURCE_PLL
* - CRM_CLOCK_SOURCE_LEXT
* - CRM_CLOCK_SOURCE_LICK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
{
switch(source)
{
case CRM_CLOCK_SOURCE_HICK:
CRM->ctrl_bit.hicken = new_state;
break;
case CRM_CLOCK_SOURCE_HEXT:
CRM->ctrl_bit.hexten = new_state;
break;
case CRM_CLOCK_SOURCE_PLL:
CRM->ctrl_bit.pllen = new_state;
break;
case CRM_CLOCK_SOURCE_LEXT:
CRM->bpdc_bit.lexten = new_state;
break;
case CRM_CLOCK_SOURCE_LICK:
CRM->ctrlsts_bit.licken = new_state;
break;
default: break;
}
}
/**
* @brief clear the crm reset flags
* @param flag
* this parameter can be one of the following values:
* reset flag:
* - CRM_PIN_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* - CRM_ALL_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval none
*/
void crm_flag_clear(uint32_t flag)
{
switch(flag)
{
case CRM_NRST_RESET_FLAG:
case CRM_POR_RESET_FLAG:
case CRM_SW_RESET_FLAG:
case CRM_WDT_RESET_FLAG:
case CRM_WWDT_RESET_FLAG:
case CRM_LOWPOWER_RESET_FLAG:
case CRM_ALL_RESET_FLAG:
CRM->ctrlsts_bit.rstfc = TRUE;
while(CRM->ctrlsts_bit.rstfc == TRUE);
break;
case CRM_LICK_READY_INT_FLAG:
CRM->clkint_bit.lickstblfc = TRUE;
break;
case CRM_LEXT_READY_INT_FLAG:
CRM->clkint_bit.lextstblfc = TRUE;
break;
case CRM_HICK_READY_INT_FLAG:
CRM->clkint_bit.hickstblfc = TRUE;
break;
case CRM_HEXT_READY_INT_FLAG:
CRM->clkint_bit.hextstblfc = TRUE;
break;
case CRM_PLL_READY_INT_FLAG:
CRM->clkint_bit.pllstblfc = TRUE;
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
CRM->clkint_bit.cfdfc = TRUE;
break;
default:
break;
}
}
/**
* @brief select ertc clock
* @param value
* this parameter can be one of the following values:
* - CRM_ERTC_CLOCK_NOCLK
* - CRM_ERTC_CLOCK_LEXT
* - CRM_ERTC_CLOCK_LICK
* - CRM_ERTC_CLOCK_HEXT_DIV_2
* - CRM_ERTC_CLOCK_HEXT_DIV_3
* - CRM_ERTC_CLOCK_HEXT_DIV_4
* - CRM_ERTC_CLOCK_HEXT_DIV_5
* - CRM_ERTC_CLOCK_HEXT_DIV_6
* - CRM_ERTC_CLOCK_HEXT_DIV_7
* - CRM_ERTC_CLOCK_HEXT_DIV_8
* - CRM_ERTC_CLOCK_HEXT_DIV_9
* - CRM_ERTC_CLOCK_HEXT_DIV_10
* - CRM_ERTC_CLOCK_HEXT_DIV_11
* - CRM_ERTC_CLOCK_HEXT_DIV_12
* - CRM_ERTC_CLOCK_HEXT_DIV_13
* - CRM_ERTC_CLOCK_HEXT_DIV_14
* - CRM_ERTC_CLOCK_HEXT_DIV_15
* - CRM_ERTC_CLOCK_HEXT_DIV_16
* - CRM_ERTC_CLOCK_HEXT_DIV_17
* - CRM_ERTC_CLOCK_HEXT_DIV_18
* - CRM_ERTC_CLOCK_HEXT_DIV_19
* - CRM_ERTC_CLOCK_HEXT_DIV_20
* - CRM_ERTC_CLOCK_HEXT_DIV_21
* - CRM_ERTC_CLOCK_HEXT_DIV_22
* - CRM_ERTC_CLOCK_HEXT_DIV_23
* - CRM_ERTC_CLOCK_HEXT_DIV_24
* - CRM_ERTC_CLOCK_HEXT_DIV_25
* - CRM_ERTC_CLOCK_HEXT_DIV_26
* - CRM_ERTC_CLOCK_HEXT_DIV_27
* - CRM_ERTC_CLOCK_HEXT_DIV_28
* - CRM_ERTC_CLOCK_HEXT_DIV_29
* - CRM_ERTC_CLOCK_HEXT_DIV_30
* - CRM_ERTC_CLOCK_HEXT_DIV_31
* @retval none
*/
void crm_ertc_clock_select(crm_ertc_clock_type value)
{
CRM->cfg_bit.ertcdiv = ((value & 0x1F0) >> 4);
CRM->bpdc_bit.ertcsel = (value & 0xF);
}
/**
* @brief enable or disable ertc
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_ertc_clock_enable(confirm_state new_state)
{
CRM->bpdc_bit.ertcen = new_state;
}
/**
* @brief set crm ahb division
* @param value
* this parameter can be one of the following values:
* - CRM_AHB_DIV_1
* - CRM_AHB_DIV_2
* - CRM_AHB_DIV_4
* - CRM_AHB_DIV_8
* - CRM_AHB_DIV_16
* - CRM_AHB_DIV_64
* - CRM_AHB_DIV_128
* - CRM_AHB_DIV_256
* - CRM_AHB_DIV_512
* @retval none
*/
void crm_ahb_div_set(crm_ahb_div_type value)
{
CRM->cfg_bit.ahbdiv = value;
}
/**
* @brief set crm apb1 division
* @param value
* this parameter can be one of the following values:
* - CRM_APB1_DIV_1
* - CRM_APB1_DIV_2
* - CRM_APB1_DIV_4
* - CRM_APB1_DIV_8
* - CRM_APB1_DIV_16
* @retval none
*/
void crm_apb1_div_set(crm_apb1_div_type value)
{
CRM->cfg_bit.apb1div = value;
}
/**
* @brief set crm apb2 division
* @param value
* this parameter can be one of the following values:
* - CRM_APB2_DIV_1
* - CRM_APB2_DIV_2
* - CRM_APB2_DIV_4
* - CRM_APB2_DIV_8
* - CRM_APB2_DIV_16
* @retval none
*/
void crm_apb2_div_set(crm_apb2_div_type value)
{
CRM->cfg_bit.apb2div = value;
}
/**
* @brief set usb division
* @param value
* this parameter can be one of the following values:
* - CRM_USB_DIV_1_5
* - CRM_USB_DIV_1
* - CRM_USB_DIV_2_5
* - CRM_USB_DIV_2
* - CRM_USB_DIV_3_5
* - CRM_USB_DIV_3
* - CRM_USB_DIV_4_5
* - CRM_USB_DIV_4
* - CRM_USB_DIV_5_5
* - CRM_USB_DIV_5
* - CRM_USB_DIV_6_5
* - CRM_USB_DIV_6
* - CRM_USB_DIV_7
* @retval none
*/
void crm_usb_clock_div_set(crm_usb_div_type value)
{
CRM->misc2_bit.usbdiv = value;
}
/**
* @brief enable or disable clock failure detection
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_failure_detection_enable(confirm_state new_state)
{
CRM->ctrl_bit.cfden = new_state;
}
/**
* @brief battery powered domain software reset
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_battery_powered_domain_reset(confirm_state new_state)
{
CRM->bpdc_bit.bpdrst = new_state;
}
/**
* @brief auto step clock switch enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_auto_step_mode_enable(confirm_state new_state)
{
if(new_state == TRUE)
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
else
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
/**
* @brief config hick divider select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK48_DIV6
* - CRM_HICK48_NODIV
* @retval none
*/
void crm_hick_divider_select(crm_hick_div_6_type value)
{
CRM->misc1_bit.hickdiv = value;
}
/**
* @brief hick as system clock frequency select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK_SCLK_8MHZ
* - CRM_HICK_SCLK_48MHZ
* @retval none
*/
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
{
crm_hick_divider_select(CRM_HICK48_NODIV);
CRM->misc1_bit.hick_to_sclk = value;
}
/**
* @brief usb 48 mhz clock source select
* @param value
* this parameter can be one of the following values:
* - CRM_USB_CLOCK_SOURCE_PLL
* - CRM_USB_CLOCK_SOURCE_HICK
* @retval none
*/
void crm_usb_clock_source_select(crm_usb_clock_source_type value)
{
if(value == CRM_USB_CLOCK_SOURCE_HICK)
{
crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
}
CRM->misc1_bit.hick_to_usb = value;
}
/**
* @brief enable or disable clkout direct to tmr10 channel 1
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clkout_to_tmr10_enable(confirm_state new_state)
{
CRM->misc2_bit.clk_to_tmr = new_state;
}
/**
* @brief config crm pll
* pll_rcs_freq * pll_ns
* pll clock = --------------------------------
* pll_ms * pll_fr_n
* attemtion:
* 31 <= pll_ns <= 500
* 1 <= pll_ms <= 15
*
* pll_rcs_freq
* 2mhz <= ---------------------- <= 16mhz
* pll_ms
*
* pll_rcs_freq * pll_ns
* 500mhz <= -------------------------------- <= 1000mhz
* pll_ms
* @param clock_source
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* @param pll_ns (31~500)
* @param pll_ms (1~15)
* @param pll_fr
* this parameter can be one of the following values:
* - CRM_PLL_FR_1
* - CRM_PLL_FR_2
* - CRM_PLL_FR_4
* - CRM_PLL_FR_8
* - CRM_PLL_FR_16
* - CRM_PLL_FR_32
* @retval none
*/
void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
uint16_t pll_ms, crm_pll_fr_type pll_fr)
{
/* config pll clock source */
CRM->pllcfg_bit.pllrcs = clock_source;
/* config pll multiplication factor */
CRM->pllcfg_bit.pllns = pll_ns;
CRM->pllcfg_bit.pllms = pll_ms;
CRM->pllcfg_bit.pllfr = pll_fr;
}
/**
* @brief select system clock source
* @param value
* this parameter can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
* @retval none
*/
void crm_sysclk_switch(crm_sclk_type value)
{
CRM->cfg_bit.sclksel = value;
}
/**
* @brief indicate which clock source is used as system clock
* @param none
* @retval crm_sclk
* this return can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
*/
crm_sclk_type crm_sysclk_switch_status_get(void)
{
return (crm_sclk_type)CRM->cfg_bit.sclksts;
}
/**
* @brief get crm clocks freqency
* @param clocks_struct
* - pointer to the crm_clocks_freq_type structure
* @retval none
*/
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
{
uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
uint32_t temp = 0, div_value = 0;
crm_sclk_type sclk_source;
static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
case CRM_SCLK_HICK:
if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
clocks_struct->sclk_freq = HICK_VALUE * 6;
else
clocks_struct->sclk_freq = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
clocks_struct->sclk_freq = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
/* get pll clock source */
pll_clock_source = CRM->pllcfg_bit.pllrcs;
/* get multiplication factor */
pll_ns = CRM->pllcfg_bit.pllns;
pll_ms = CRM->pllcfg_bit.pllms;
pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
if (pll_clock_source == CRM_PLL_SOURCE_HICK)
{
/* hick selected as pll clock entry */
pllrcsfreq = HICK_VALUE;
}
else
{
/* hext selected as pll clock entry */
pllrcsfreq = HEXT_VALUE;
}
clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * pll_fr));
break;
default:
clocks_struct->sclk_freq = HICK_VALUE;
break;
}
/* compute sclk, ahbclk, abp1clk and apb2clk frequencies */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sclk_ahb_div_table[temp];
/* ahbclk frequency */
clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
/* get apb1 division */
temp = CRM->cfg_bit.apb1div;
div_value = ahb_apb1_div_table[temp];
/* apb1clk frequency */
clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
/* get apb2 division */
temp = CRM->cfg_bit.apb2div;
div_value = ahb_apb2_div_table[temp];
/* apb2clk frequency */
clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
}
/**
* @brief set crm clkout1
* @param clkout
* this parameter can be one of the following values:
* - CRM_CLKOUT1_HICK
* - CRM_CLKOUT1_LEXT
* - CRM_CLKOUT1_HEXT
* - CRM_CLKOUT1_PLL
* @retval none
*/
void crm_clock_out1_set(crm_clkout1_select_type clkout)
{
CRM->cfg_bit.clkout1_sel = clkout;
}
/**
* @brief set crm clkout2
* @param clkout
* this parameter can be one of the following values:
* - CRM_CLKOUT2_SCLK
* - CRM_CLKOUT2_HEXT
* - CRM_CLKOUT2_PLL
* - CRM_CLKOUT2_USB
* - CRM_CLKOUT2_ADC
* - CRM_CLKOUT2_HICK
* - CRM_CLKOUT2_LICK
* - CRM_CLKOUT2_LEXT
* @retval none
*/
void crm_clock_out2_set(crm_clkout2_select_type clkout)
{
if(clkout < 0x10)
{
CRM->cfg_bit.clkout2_sel1 = (clkout & 0x3);
}
else
{
CRM->cfg_bit.clkout2_sel1 = 0x1;
CRM->misc1_bit.clkout2_sel2 = (clkout & 0xF);
}
}
/**
* @brief set crm clkout1 division1
* @param div1
* this parameter can be one of the following values:
* - CRM_CLKOUT_INDEX_1
* - CRM_CLKOUT_INDEX_2
* @param div1
* this parameter can be one of the following values:
* - CRM_CLKOUT_DIV1_1
* - CRM_CLKOUT_DIV1_2
* - CRM_CLKOUT_DIV1_3
* - CRM_CLKOUT_DIV1_4
* - CRM_CLKOUT_DIV1_5
* @param div2
* this parameter can be one of the following values:
* - CRM_CLKOUT_DIV2_1
* - CRM_CLKOUT_DIV2_2
* - CRM_CLKOUT_DIV2_4
* - CRM_CLKOUT_DIV2_8
* - CRM_CLKOUT_DIV2_16
* - CRM_CLKOUT_DIV2_64
* - CRM_CLKOUT_DIV2_128
* - CRM_CLKOUT_DIV2_256
* - CRM_CLKOUT_DIV2_512
* @retval none
*/
void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2)
{
if(index == CRM_CLKOUT_INDEX_1)
{
CRM->cfg_bit.clkout1div1 = div1;
CRM->misc1_bit.clkout1div2 = div2;
}
else
{
CRM->cfg_bit.clkout2div1 = div1;
CRM->misc1_bit.clkout2div2 = div2;
}
}
/**
* @brief set emac output pulse width
* @param width
* this parameter can be one of the following values:
* - CRM_EMAC_PULSE_125MS
* - CRM_EMAC_PULSE_1SCLK
* @retval none
*/
void crm_emac_output_pulse_set(crm_emac_output_pulse_type width)
{
CRM->misc2_bit.emac_pps_sel = width;
}
/**
* @brief config crm interrupt
* @param int
* this parameter can be any combination of the following values:
* - CRM_LICK_STABLE_INT
* - CRM_LEXT_STABLE_INT
* - CRM_HICK_STABLE_INT
* - CRM_HEXT_STABLE_INT
* - CRM_PLL_STABLE_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
{
if(TRUE == new_state)
CRM->clkint |= crm_int;
else
CRM->clkint &= ~crm_int;
}
/**
* @brief calculate the pll parameters with pll reference clock and target pll output frequency.
* pll_rcs_freq * pll_ns
* pll clock = --------------------------------
* pll_ms * pll_fr_n
* attemtion:
* 31 <= pll_ns <= 500
* 1 <= pll_ms <= 15
*
* pll_rcs_freq
* 2mhz <= ---------------------- <= 16mhz
* pll_ms
*
* pll_rcs_freq * pll_ns
* 500mhz <= -------------------------------- <= 1000mhz
* pll_ms
* @param pll_rcs
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* @param target_sclk_freq: target pll output frequency, such as 200 mhz (target_sclk_freq: 200000000)
* @param ret_ms: pointer to ms value, return the pll_ms of pll parameters
* @param ret_ns: pointer to ns value, return the pll_ns of pll parameters
* @param ret_fr: pointer to fr value, return the pll_fr of pll parameters
* @retval error_status (SUCCESS or ERROR)
*/
error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr)
{
uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0;
uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF;
uint32_t result = 0, absolute_value = 0;
/* reduce calculate accuracy, target_sclk_freq accuracy with khz */
target_sclk_freq = target_sclk_freq / 1000;
/* get pll reference clock frequency, accuracy with khz */
if(pll_rcs == CRM_PLL_SOURCE_HICK)
pll_rcs_freq = HICK_VALUE / 1000;
else
pll_rcs_freq = HEXT_VALUE / 1000;
/* polling ms range, accuracy with khz */
for(ms = 1; ms <= 15; ms ++)
{
result = pll_rcs_freq / ms;
if((result >= 2000U) && (result <= 16000U))
{
if(ms_min == 0)
ms_min = ms;
ms_max = ms;
}
}
/* polling pll parameters */
for(ms = ms_min; ms <= ms_max; ms ++)
{
for(fr = 0; fr <= 5; fr ++)
{
for(ns = 31; ns <= 500; ns ++)
{
result = (pll_rcs_freq * ns) / (ms);
/* check vco frequency range, accuracy with khz */
if((result < 500000U) || (result > 1000000U))
{
continue;
}
/* calculate pll output frequency */
result = result / (0x1 << fr);
/* check frequency */
if(target_sclk_freq == result)
{
*ret_ms = ms;
*ret_ns = ns;
*ret_fr = fr;
/* the pll parameters that is equal to target_sclk_freq */
return SUCCESS;
}
/* calculate error range, accuracy with khz */
absolute_value = (result > target_sclk_freq) ? (result - target_sclk_freq) : (target_sclk_freq - result);
if(absolute_value < error_min)
{
error_min = absolute_value;
*ret_ms = ms;
*ret_ns = ns;
*ret_fr = fr;
}
}
}
}
/* the pll parameters that is the closest approach to target_sclk_freq */
return ERROR;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_dac.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
#ifdef DAC_MODULE_ENABLED
/** @defgroup DAC_private_functions
* @{
*/
/**
* @brief dac reset
* @param none
* @retval none
*/
void dac_reset(void)
{
crm_periph_reset(CRM_DAC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_DAC_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable dac
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1en = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2en = new_state;
break;
default:
break;
}
}
/**
* @brief enable or disable dac output buffer
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state)
{
new_state = (confirm_state)!new_state;
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1obdis = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2obdis = new_state;
break;
default:
break;
}
}
/**
* @brief enable or disable dac trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1trgen = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2trgen = new_state;
break;
default:
break;
}
}
/**
* @brief select dac trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_trigger_source
* this parameter can be one of the following values:
* - DAC_TMR6_TRGOUT_EVENT
* - DAC_TMR8_TRGOUT_EVENT
* - DAC_TMR7_TRGOUT_EVENT
* - DAC_TMR5_TRGOUT_EVENT
* - DAC_TMR2_TRGOUT_EVENT
* - DAC_TMR4_TRGOUT_EVENT
* - DAC_EXTERNAL_INTERRUPT_LINE_9
* - DAC_SOFTWARE_TRIGGER
* @retval none
*/
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1trgsel = dac_trigger_source;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2trgsel = dac_trigger_source;
break;
default:
break;
}
}
/**
* @brief generate dac software trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval none
*/
void dac_software_trigger_generate(dac_select_type dac_select)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->swtrg_bit.d1swtrg = TRUE;
break;
case DAC2_SELECT:
DAC->swtrg_bit.d2swtrg = TRUE;
break;
default:
break;
}
}
/**
* @brief generate dac dual software trigger synchronously
* @param none
* @retval none
*/
void dac_dual_software_trigger_generate(void)
{
DAC->swtrg |= 0x03;
}
/**
* @brief generate dac wave
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_wave
* this parameter can be one of the following values:
* - DAC_WAVE_GENERATE_NONE
* - DAC_WAVE_GENERATE_NOISE
* - DAC_WAVE_GENERATE_TRIANGLE
* @retval none
*/
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1nm = dac_wave;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2nm = dac_wave;
break;
default:
break;
}
}
/**
* @brief select dac mask amplitude
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_mask_amplitude
* this parameter can be one of the following values:
* - DAC_LSFR_BIT0_AMPLITUDE_1
* - DAC_LSFR_BIT10_AMPLITUDE_3
* - DAC_LSFR_BIT20_AMPLITUDE_7
* - DAC_LSFR_BIT30_AMPLITUDE_15
* - DAC_LSFR_BIT40_AMPLITUDE_31
* - DAC_LSFR_BIT50_AMPLITUDE_63
* - DAC_LSFR_BIT60_AMPLITUDE_127
* - DAC_LSFR_BIT70_AMPLITUDE_255
* - DAC_LSFR_BIT80_AMPLITUDE_511
* - DAC_LSFR_BIT90_AMPLITUDE_1023
* - DAC_LSFR_BITA0_AMPLITUDE_2047
* - DAC_LSFR_BITB0_AMPLITUDE_4095
* @retval none
*/
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1nbsel = dac_mask_amplitude;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2nbsel = dac_mask_amplitude;
break;
default:
break;
}
}
/**
* @brief enable or disable dac dma
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1dmaen = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2dmaen = new_state;
break;
default:
break;
}
}
/**
* @brief get dac data output
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval dac channel data output
*/
uint16_t dac_data_output_get(dac_select_type dac_select)
{
uint16_t data_output =0;
switch(dac_select)
{
case DAC1_SELECT:
data_output = DAC->d1odt_bit.d1odt;
break;
case DAC2_SELECT:
data_output = DAC->d2odt_bit.d2odt;
break;
default:
break;
}
return data_output;
}
/**
* @brief set dac1 data
* @param dac1_aligned
* this parameter can be one of the following values:
* DAC1_12BIT_RIGHT
* DAC1_12BIT_LEFT
* DAC1_8BIT_RIGHT
* @param dac1_data :indecate from selected data holding register
* @retval none
*/
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data)
{
*(__IO uint32_t *) dac1_aligned = dac1_data;
}
/**
* @brief set dac2 data
* @param dac2_aligned
* this parameter can be one of the following values:
* DAC2_12BIT_RIGHT
* DAC2_12BIT_LEFT
* DAC2_8BIT_RIGHT
* @param dac2_data :indecate from selected data holding register
* @retval none
*/
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data)
{
*(__IO uint32_t *) dac2_aligned = dac2_data;
}
/**
* @brief set dac dual data
* @param dac_dual
* this parameter can be one of the following values:
* DAC_DUAL_12BIT_RIGHT
* DAC_DUAL_12BIT_LEFT
* DAC_DUAL_8BIT_RIGHT
* @param data1 :dac1 channel indecate from selected data holding register
* @param data2 :dac1 channel indecate from selected data holding register
* @retval none
*/
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2)
{
switch(dac_dual)
{
case DAC_DUAL_12BIT_RIGHT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
break;
case DAC_DUAL_12BIT_LEFT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
break;
case DAC_DUAL_8BIT_RIGHT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 8));
break;
default:
break;
}
}
/**
* @brief enable/disable dac dma udr interrupt
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_udr_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1dmaudrien = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2dmaudrien = new_state;
break;
default:
break;
}
}
/**
* @brief get flag of the dac udr flag.
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval the new state of dac udr flag status(SET or RESET).
*/
flag_status dac_udr_flag_get(dac_select_type dac_select)
{
flag_status status = RESET;
switch(dac_select)
{
case DAC1_SELECT:
if(DAC->sts_bit.d1dmaudrf != 0)
status = SET;
break;
case DAC2_SELECT:
if(DAC->sts_bit.d2dmaudrf != 0)
status = SET;
break;
default:
break;
}
return status;
}
/**
* @brief clear the dac udr flag.
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval none
*/
void dac_udr_flag_clear(dac_select_type dac_select)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->sts = DAC1_D1DMAUDRF;
break;
case DAC2_SELECT:
DAC->sts = DAC2_D2DMAUDRF;
break;
default:
break;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_mcudbg.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the mcudbg firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup DEBUG
* @brief DEBUG driver modules
* @{
*/
#ifdef DEBUG_MODULE_ENABLED
/** @defgroup DEBUG_private_functions
* @{
*/
/**
* @brief get debug device id
* @param none
* @retval the debug device id
*/
uint32_t debug_device_id_get(void)
{
return DEBUGMCU->pid;
}
/**
* @brief set periph debug mode
* @param periph_debug_mode
* this parameter can be one of the following values:
* - DEBUG_SLEEP
* - DEBUG_DEEPSLEEP
* - DEBUG_STANDBY
* @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUGMCU->ctrl |= low_power_mode;
}
else
{
DEBUGMCU->ctrl &= ~low_power_mode;
}
}
/**
* @brief set apb1 periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_TMR2_PAUSE - DEBUG_TMR3_PAUSE
* - DEBUG_TMR4_PAUSE - DEBUG_TMR5_PAUSE
* - DEBUG_TMR6_PAUSE - DEBUG_TMR7_PAUSE
* - DEBUG_TMR12_PAUSE - DEBUG_TMR13_PAUSE
* - DEBUG_TMR14_PAUSE - DEBUG_ERTC_PAUSE
* - DEBUG_WWDT_PAUSE - DEBUG_WDT_PAUSE
* - DEBUG_ERTC_512_PAUSE - DEBUG_I2C1_SMBUS_TIMEOUT
* - DEBUG_I2C2_SMBUS_TIMEOUT - DEBUG_I2C3_SMBUS_TIMEOUT
* - DEBUG_CAN1_PAUSE - DEBUG_CAN2_PAUSE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUGMCU->apb1_frz |= apb1_periph;
}
else
{
DEBUGMCU->apb1_frz &= ~apb1_periph;
}
}
/**
* @brief set apb2 periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_TMR1_PAUSE - DEBUG_TMR8_PAUSE
* - DEBUG_TMR20_PAUSE - DEBUG_TMR9_PAUSE
* - DEBUG_TMR10_PAUSE - DEBUG_TMR11_PAUSE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUGMCU->apb2_frz |= apb2_periph;
}
else
{
DEBUGMCU->apb2_frz &= ~apb2_periph;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_dma.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
#ifdef DMA_MODULE_ENABLED
/** @defgroup DMA_private_functions
* @{
*/
/**
* @brief reset dmax channely register.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @retval none.
*/
void dma_reset(dma_channel_type *dmax_channely)
{
uint32_t temp = 0;
dmax_channely->ctrl_bit.chen = FALSE;
dmax_channely->ctrl = 0;
dmax_channely->dtcnt = 0;
dmax_channely->paddr = 0;
dmax_channely->maddr = 0;
temp = (uint32_t)dmax_channely;
if((temp & 0x6FF) < 0x608)
{
/* dma1 channel */
DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
}
else if((temp & 0x6FF) < 0x688)
{
/* dma2 channel */
DMA2->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
}
}
/**
* @brief set the number of data to be transferred.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param data_number: the number of data to be transferred (0x0000~0xFFFF).
* @retval none.
*/
void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number)
{
dmax_channely->dtcnt = data_number;
}
/**
* @brief get the number of data to be transferred.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @retval the number value.
*/
uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
{
return (uint16_t)dmax_channely->dtcnt;
}
/**
* @brief enable or disable dma interrupt.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param dma_int:
* this parameter can be any combination of the following values:
* - DMA_FDT_INT
* - DMA_HDT_INT
* - DMA_DTERR_INT
* @param new_state (TRUE or FALSE)
* @retval none.
*/
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
{
if(new_state != FALSE)
{
dmax_channely->ctrl |= dma_int;
}
else
{
dmax_channely->ctrl &= ~dma_int;
}
}
/**
* @brief enable or disable dma channel.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state)
{
dmax_channely->ctrl_bit.chen = new_state;
}
/**
* @brief dma flag get.
* @param dma_flag
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval state of dma flag.
*/
flag_status dma_flag_get(uint32_t dmax_flag)
{
uint32_t temp = 0;
if(dmax_flag > 0x10000000)
{
temp = DMA2->sts;
}
else
{
temp = DMA1->sts;
}
if((temp & dmax_flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief dma flag clear.
* @param dma_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval none.
*/
void dma_flag_clear(uint32_t dmax_flag)
{
if(dmax_flag > ((uint32_t)0x10000000))
{
DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
}
else
{
DMA1->clr = dmax_flag;
}
}
/**
* @brief dma init config with its default value.
* @param dma_init_struct: pointer to a dma_init_type structure which will be initialized.
* @retval none.
*/
void dma_default_para_init(dma_init_type *dma_init_struct)
{
dma_init_struct->peripheral_base_addr = 0;
dma_init_struct->memory_base_addr = 0;
dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct->buffer_size = 0;
dma_init_struct->peripheral_inc_enable = FALSE;
dma_init_struct->memory_inc_enable = FALSE;
dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct->loop_mode_enable = FALSE;
dma_init_struct->priority = DMA_PRIORITY_LOW;
}
/**
* @brief dma init.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param dma_init_struct: pointer to a dma_init_type structure.
* @retval none.
*/
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
{
/* clear ctrl register dtd bit and m2m bit */
dmax_channely->ctrl &= 0xbfef;
dmax_channely->ctrl |= dma_init_struct->direction;
dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
dmax_channely->maddr = dma_init_struct->memory_base_addr;
}
/**
* @brief dmamux init.
* @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
* @param dmamux_channelx:
* this parameter can be one of the following values:
* - DMA1MUX_CHANNEL1
* - DMA1MUX_CHANNEL2
* - DMA1MUX_CHANNEL3
* - DMA1MUX_CHANNEL4
* - DMA1MUX_CHANNEL5
* - DMA1MUX_CHANNEL6
* - DMA1MUX_CHANNEL7
* - DMA2MUX_CHANNEL1
* - DMA2MUX_CHANNEL2
* - DMA2MUX_CHANNEL3
* - DMA2MUX_CHANNEL4
* - DMA2MUX_CHANNEL5
* - DMA2MUX_CHANNEL6
* - DMA2MUX_CHANNEL7
* @param dmamux_req_sel:
* this parameter can be one of the following values:
* - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
* - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
* - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
* - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
* - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
* - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
* - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
* - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
* - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
* - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
* - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
* - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
* - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
* - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
* - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
* - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
* - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
* - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
* - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
* - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
* - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
* @retval none.
*/
void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
{
dma_x->muxsel_bit.tblsel = TRUE;
dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
}
/**
* @brief enable or disable the dmamux.
* @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
* @param new_state (TRUE or FALSE) .
* @retval none.
*/
void dmamux_enable(dma_type *dma_x, confirm_state new_state)
{
dma_x->muxsel_bit.tblsel = new_state;
}
/**
* @brief dmamux init.
* @param dmamux_channelx:
* this parameter can be one of the following values:
* - DMA1MUX_CHANNEL1
* - DMA1MUX_CHANNEL2
* - DMA1MUX_CHANNEL3
* - DMA1MUX_CHANNEL4
* - DMA1MUX_CHANNEL5
* - DMA1MUX_CHANNEL6
* - DMA1MUX_CHANNEL7
* - DMA2MUX_CHANNEL1
* - DMA2MUX_CHANNEL2
* - DMA2MUX_CHANNEL3
* - DMA2MUX_CHANNEL4
* - DMA2MUX_CHANNEL5
* - DMA2MUX_CHANNEL6
* - DMA2MUX_CHANNEL7
* @param dmamux_req_sel:
* this parameter can be one of the following values:
* - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
* - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
* - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
* - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
* - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
* - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
* - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
* - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
* - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
* - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
* - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
* - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
* - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
* - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
* - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
* - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
* - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
* - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
* - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
* - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
* - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
* - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
* @retval none.
*/
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
{
dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
}
/**
* @brief dmamux sync init struct config with its default value.
* @param dmamux_sync_init_struct: pointer to a dmamux_sync_init_type structure which will be initialized.
* @retval none.
*/
void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct)
{
dmamux_sync_init_struct->sync_enable = FALSE;
dmamux_sync_init_struct->sync_event_enable = FALSE;
dmamux_sync_init_struct->sync_polarity = DMAMUX_SYNC_POLARITY_DISABLE;
dmamux_sync_init_struct->sync_request_number = 0x0;
dmamux_sync_init_struct->sync_signal_sel = (dmamux_sync_id_sel_type)0;
}
/**
* @brief dmamux synchronization config.
* @param dmamux_channelx:
* this parameter can be one of the following values:
* - DMA1MUX_CHANNEL1
* - DMA1MUX_CHANNEL2
* - DMA1MUX_CHANNEL3
* - DMA1MUX_CHANNEL4
* - DMA1MUX_CHANNEL5
* - DMA1MUX_CHANNEL6
* - DMA1MUX_CHANNEL7
* - DMA2MUX_CHANNEL1
* - DMA2MUX_CHANNEL2
* - DMA2MUX_CHANNEL3
* - DMA2MUX_CHANNEL4
* - DMA2MUX_CHANNEL5
* - DMA2MUX_CHANNEL6
* - DMA2MUX_CHANNEL7
* @param dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
* @retval none.
*/
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
{
dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number;
dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable;
dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
}
/**
* @brief dmamux request generator init struct config with its default value.
* @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
* @retval none.
*/
void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct)
{
dmamux_gen_init_struct->gen_enable = FALSE;
dmamux_gen_init_struct->gen_polarity = DMAMUX_GEN_POLARITY_DISABLE;
dmamux_gen_init_struct->gen_request_number = 0x0;
dmamux_gen_init_struct->gen_signal_sel = (dmamux_gen_id_sel_type)0x0;
}
/**
* @brief dmamux request generator init.
* @param dmamux_gen_x :
* this parameter can be one of the following values:
* - DMA1MUX_GENERATOR1
* - DMA1MUX_GENERATOR2
* - DMA1MUX_GENERATOR3
* - DMA1MUX_GENERATOR4
* - DMA2MUX_GENERATOR1
* - DMA2MUX_GENERATOR2
* - DMA2MUX_GENERATOR3
* - DMA2MUX_GENERATOR4
* @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
* @retval none.
*/
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
{
dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel;
dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity;
dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number;
dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable;
}
/**
* @brief enable or disable the dmamux sync interrupts.
* @param dmamux_channelx:
* this parameter can be one of the following values:
* - DMA1MUX_CHANNEL1
* - DMA1MUX_CHANNEL2
* - DMA1MUX_CHANNEL3
* - DMA1MUX_CHANNEL4
* - DMA1MUX_CHANNEL5
* - DMA1MUX_CHANNEL6
* - DMA1MUX_CHANNEL7
* - DMA2MUX_CHANNEL1
* - DMA2MUX_CHANNEL2
* - DMA2MUX_CHANNEL3
* - DMA2MUX_CHANNEL4
* - DMA2MUX_CHANNEL5
* - DMA2MUX_CHANNEL6
* - DMA2MUX_CHANNEL7
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state)
{
if(new_state != FALSE)
{
dmamux_channelx->muxctrl_bit.syncovien = TRUE;
}
else
{
dmamux_channelx->muxctrl_bit.syncovien = FALSE;
}
}
/**
* @brief enable or disable the dmamux request generator interrupts.
* @param dmamux_gen_x : pointer to a dmamux_generator_type structure.
* this parameter can be one of the following values:
* - DMA1MUX_GENERATOR1
* - DMA1MUX_GENERATOR2
* - DMA1MUX_GENERATOR3
* - DMA1MUX_GENERATOR4
* - DMA2MUX_GENERATOR1
* - DMA2MUX_GENERATOR2
* - DMA2MUX_GENERATOR3
* - DMA2MUX_GENERATOR4
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state)
{
if(new_state != FALSE)
{
dmamux_gen_x->gctrl_bit.trgovien = TRUE;
}
else
{
dmamux_gen_x->gctrl_bit.trgovien = FALSE;
}
}
/**
* @brief dmamux sync flag get.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_SYNC_OV1_FLAG
* - DMAMUX_SYNC_OV2_FLAG
* - DMAMUX_SYNC_OV3_FLAG
* - DMAMUX_SYNC_OV4_FLAG
* - DMAMUX_SYNC_OV5_FLAG
* - DMAMUX_SYNC_OV6_FLAG
* - DMAMUX_SYNC_OV7_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
{
if((dma_x->muxsyncsts & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief dmamux sync flag clear.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_SYNC_OV1_FLAG
* - DMAMUX_SYNC_OV2_FLAG
* - DMAMUX_SYNC_OV3_FLAG
* - DMAMUX_SYNC_OV4_FLAG
* - DMAMUX_SYNC_OV5_FLAG
* - DMAMUX_SYNC_OV6_FLAG
* - DMAMUX_SYNC_OV7_FLAG
* @retval none.
*/
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
{
dma_x->muxsyncclr = flag;
}
/**
* @brief dmamux request generator flag get.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_GEN_TRIG_OV1_FLAG
* - DMAMUX_GEN_TRIG_OV2_FLAG
* - DMAMUX_GEN_TRIG_OV3_FLAG
* - DMAMUX_GEN_TRIG_OV4_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
{
if((dma_x->muxgsts & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief dmamux request generator flag clear.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_GEN_TRIG_OV1_FLAG
* - DMAMUX_GEN_TRIG_OV2_FLAG
* - DMAMUX_GEN_TRIG_OV3_FLAG
* - DMAMUX_GEN_TRIG_OV4_FLAG
* @retval none.
*/
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
{
dma_x->muxgclr = flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_dvp.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dvp firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup DVP
* @brief DVP driver modules
* @{
*/
#ifdef DVP_MODULE_ENABLED
/** @defgroup DVP_private_functions
* @{
*/
/**
* @brief reset the dvp register
* @param none
* @retval none
*/
void dvp_reset(void)
{
crm_periph_reset(CRM_DVP_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_DVP_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable dvp capture
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_capture_enable(confirm_state new_state)
{
DVP->ctrl_bit.cap = new_state;
}
/**
* @brief set dvp capture mode
* @param cap_mode
* this parameter can be one of the following values:
* - DVP_CAP_FUNC_MODE_CONTINUOUS
* - DVP_CAP_FUNC_MODE_SINGLE
* @retval none
*/
void dvp_capture_mode_set(dvp_cfm_type cap_mode)
{
DVP->ctrl_bit.cfm = cap_mode;
}
/**
* @brief set dvp cropping window enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_window_crop_enable(confirm_state new_state)
{
DVP->ctrl_bit.crp = new_state;
}
/**
* @brief set dvp cropping window configuration
* @param crop_x: cropping window horizontal start pixel
* @param crop_y: cropping window vertical start line
* @param crop_w: cropping window horizontal pixel number
* @param crop_h: cropping window vertical line number
* @param bytes: the number of bytes corresponding to one pixel
* eg. y8:bytes = 1, rgb565:bytes = 2
* @retval none
*/
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes)
{
DVP->cwst = ((crop_x * bytes) | (crop_y << 16));
DVP->cwsz = ((crop_w * bytes - 1) | ((crop_h - 1) << 16));
}
/**
* @brief enable or disable dvp jpeg
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_jpeg_enable(confirm_state new_state)
{
DVP->ctrl_bit.jpeg = new_state;
}
/**
* @brief set dvp synchronization mode
* @param sync_mode
* this parameter can be one of the following values:
* - DVP_SYNC_MODE_HARDWARE
* - DVP_SYNC_MODE_EMBEDDED
* @retval none
*/
void dvp_sync_mode_set(dvp_sm_type sync_mode)
{
DVP->ctrl_bit.sm = sync_mode;
}
/**
* @brief set dvp synchronization code configuration
* @param fmsc(0x00~0xFF): frame start code
* @param fmec(0x00~0xFF): frame end code
* @param lnsc(0x00~0xFF): line start code
* @param lnec(0x00~0xFF): line end code
* @retval none
*/
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec)
{
DVP->scr = (fmsc | (lnsc << 8) | (lnec << 16) | (fmec << 24));
}
/**
* @brief set dvp synchronization unmask configuration
* @param fmsu(0x00~0xFF): frame start unmask
* @param fmeu(0x00~0xFF): frame end unmask
* @param lnsu(0x00~0xFF): line start unmask
* @param lneu(0x00~0xFF): line end unmask
* @retval none
*/
void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu)
{
DVP->sur = (fmsu | (lnsu << 8) | (lneu << 16) | (fmeu << 24));
}
/**
* @brief set dvp pixel clock polarity
* @param edge
* this parameter can be one of the following values:
* - DVP_CLK_POLARITY_RISING
* - DVP_CLK_POLARITY_FALLING
* @retval none
*/
void dvp_pclk_polarity_set(dvp_ckp_type edge)
{
DVP->ctrl_bit.ckp = edge;
}
/**
* @brief set dvp horizontal synchronization polarity
* @param hsync_pol
* this parameter can be one of the following values:
* - DVP_HSYNC_POLARITY_HIGH
* - DVP_HSYNC_POLARITY_LOW
* @retval none
*/
void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol)
{
DVP->ctrl_bit.hsp = hsync_pol;
}
/**
* @brief set dvp vertical synchronization polarity
* @param vsync_pol
* this parameter can be one of the following values:
* - DVP_VSYNC_POLARITY_LOW
* - DVP_VSYNC_POLARITY_HIGH
* @retval none
*/
void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol)
{
DVP->ctrl_bit.vsp = vsync_pol;
}
/**
* @brief config dvp basic frame rate control
* @note this function only work in continuous fire mode(ctrl_bit.cfm = 0)
* @param dvp_bfrc
* this parameter can be one of the following values:
* - DVP_BFRC_ALL
* - DVP_BFRC_HALF
* - DVP_BFRC_QUARTER
* @retval none
*/
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc)
{
DVP->ctrl_bit.bfrc = dvp_bfrc;
}
/**
* @brief config dvp pixel data length
* @param dvp_pdl
* this parameter can be one of the following values:
* - DVP_PIXEL_DATA_LENGTH_8
* - DVP_PIXEL_DATA_LENGTH_10
* - DVP_PIXEL_DATA_LENGTH_12
* - DVP_PIXEL_DATA_LENGTH_14
* @retval none
*/
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl)
{
DVP->ctrl_bit.pdl = dvp_pdl;
}
/**
* @brief enable or disable dvp function
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_enable(confirm_state new_state)
{
DVP->ctrl_bit.ena = new_state;
}
/**
* @brief set dvp zoomout select
* @param dvp_pcdes: pixel capture/drop selection extension (Only work when pcdc = 2)
* this parameter can be one of the following values:
* - DVP_PCDES_CAP_FIRST
* - DVP_PCDES_DROP_FIRST
* @retval none
*/
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes)
{
DVP->actrl_bit.pcdes = dvp_pcdes;
}
/**
* @brief set dvp zoomout configuration
* @param dvp_pcdc: basic pixel capture/drop control
* this parameter can be one of the following values:
* - DVP_PCDC_ALL
* - DVP_PCDC_ONE_IN_TWO
* - DVP_PCDC_ONE_IN_FOUR
* - DVP_PCDC_TWO_IN_FOUR
* @param dvp_pcds: pixel capture/drop selection
* this parameter can be one of the following values:
* - DVP_PCDS_CAP_FIRST
* - DVP_PCDS_DROP_FIRST
* @param dvp_lcdc: line capture/drop control
* this parameter can be one of the following values:
* - DVP_LCDC_ALL
* - DVP_LCDC_ONE_IN_TWO
* @param dvp_lcds: line capture/drop selection
* this parameter can be one of the following values:
* - DVP_LCDS_CAP_FIRST
* - DVP_LCDS_DROP_FIRST
* @retval none
*/
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds)
{
DVP->ctrl_bit.pcdc = dvp_pcdc;
DVP->ctrl_bit.pcds = dvp_pcds;
DVP->ctrl_bit.lcdc = dvp_lcdc;
DVP->ctrl_bit.lcds = dvp_lcds;
}
/**
* @brief get dvp basic status
* @param dvp_status_basic_type:
* this parameter can be one of the following values:
* - DVP_STATUS_HSYN
* - DVP_STATUS_VSYN
* - DVP_STATUS_OFNE
* @retval flag_status (SET or RESET)
*/
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic)
{
flag_status status = RESET;
if ((DVP->sts & (0x1 << dvp_status_basic)) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief enable or disable dvp interrupt
* @param dvp_int:
* this parameter can be any combination of the following values:
* - DVP_CFD_INT
* - DVP_OVR_INT
* - DVP_ESE_INT
* - DVP_VS_INT
* - DVP_HS_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state)
{
if(new_state == TRUE)
{
DVP->ier |= dvp_int;
}
else
{
DVP->ier &= ~dvp_int;
}
}
/**
* @brief get dvp event/interrupt flag status
* @param flag
* this parameter can be one of the following values:
* event flag:
* - DVP_CFD_EVT_FLAG
* - DVP_OVR_EVT_FLAG
* - DVP_ESE_EVT_FLAG
* - DVP_VS_EVT_FLAG
* - DVP_HS_EVT_FLAG
* interrupt flag:
* - DVP_CFD_INT_FLAG
* - DVP_OVR_INT_FLAG
* - DVP_ESE_INT_FLAG
* - DVP_VS_INT_FLAG
* - DVP_HS_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status dvp_flag_get(uint32_t flag)
{
flag_status status = RESET;
if(flag & 0x80000000)
{
if((DVP->ists & flag) != RESET)
{
status = SET;
}
else
{
status = RESET;
}
}
else
{
if((DVP->ests & flag) != RESET)
{
status = SET;
}
else
{
status = RESET;
}
}
return status;
}
/**
* @brief clear dvp's pending flags
* @param flag
* this parameter can be one of the following values:
* event flag:
* - DVP_CFD_EVT_FLAG
* - DVP_OVR_EVT_FLAG
* - DVP_ESE_EVT_FLAG
* - DVP_VS_EVT_FLAG
* - DVP_HS_EVT_FLAG
* interrupt flag:
* - DVP_CFD_INT_FLAG
* - DVP_OVR_INT_FLAG
* - DVP_ESE_INT_FLAG
* - DVP_VS_INT_FLAG
* - DVP_HS_INT_FLAG
* @retval none
*/
void dvp_flag_clear(uint32_t flag)
{
flag &= ~0x80000000;
DVP->iclr = flag;
}
/**
* @brief set dvp enhanced image scaling resize enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_enhanced_scaling_resize_enable(confirm_state new_state)
{
DVP->actrl_bit.eisre = new_state;
}
/**
* @brief set dvp enhanced image scaling resize configuration
* @param src_w(0x0001~0x1FFF): horizontal scaling resize source size (source image width)
* @param des_w(0x0001~0x1FFF): horizontal scaling resize target size (target image width)
* @param src_h(0x0001~0x1FFF): vertical scaling resize source size (source image height)
* @param des_h(0x0001~0x1FFF): vertical scaling resize target size (target image height)
* @retval none
*/
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h)
{
if((!DVP->ctrl_bit.pcdc) && (!DVP->ctrl_bit.lcdc) && DVP->actrl_bit.efdf)
{
DVP->hscf = (src_w | (des_w << 16));
DVP->vscf = (src_h | (des_h << 16));
}
}
/**
* @brief set enhanced frame rate control configuration
* @param efrcsf(0x00~0x1F): original frame rate contorl factor
* @param efrctf(0x00~0x1F): enhanced frame rate contorl factor
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state)
{
if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrctf <= efrcsf))
{
DVP->frf = (efrcsf | (efrctf << 8));
}
DVP->actrl_bit.efrce = new_state;
}
/**
* @brief set dvp monochrome image binarization configuration
* @param mibthd(0x00~0xFF): monochrome image binarization threshold
* @param new_state: (TRUE or FALSE)
* @retval none
*/
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state)
{
DVP->bth_bit.mibthd = mibthd;
DVP->actrl_bit.mibe = new_state;
}
/**
* @brief set dvp enhanced function data format configuration
* @param dvp_efdf: enhanced function data format
* this parameter can be one of the following values:
* - DVP_EFDF_BYPASS
* - DVP_EFDF_YUV422_UYVY
* - DVP_EFDF_YUV422_YUYV
* - DVP_EFDF_RGB565_555
* - DVP_EFDF_Y8
* @retval none
*/
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf)
{
DVP->actrl_bit.efdf = dvp_efdf;
}
/**
* @brief set dvp input data un-used condition/number configuration
* @param dvp_idus: input data un-used condition
* this parameter can be one of the following values:
* - DVP_IDUS_MSB
* - DVP_IDUS_LSB
* @param dvp_idun: input data un-used number
* this parameter can be one of the following values:
* - DVP_IDUN_0
* - DVP_IDUN_2
* - DVP_IDUN_4
* - DVP_IDUN_6
* @retval none
*/
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun)
{
DVP->actrl_bit.idus = dvp_idus;
DVP->actrl_bit.idun = dvp_idun;
}
/**
* @brief set dvp dma burst transfer configuration
* @param dvp_dmabt: dma burst transfer configuration
* this parameter can be one of the following values:
* - DVP_DMABT_SINGLE
* - DVP_DMABT_BURST
* @retval none
*/
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt)
{
DVP->actrl_bit.dmabt = dvp_dmabt;
}
/**
* @brief set dvp hsync/vsync event interrupt strategy configuration
* @param dvp_hseid: hsync event interrupt strategy
* this parameter can be one of the following values:
* - DVP_HSEID_LINE_END
* - DVP_HSEID_LINE_START
* @param dvp_vseid: vsync event interrupt strategy
* this parameter can be one of the following values:
* - DVP_VSEID_FRAME_END
* - DVP_VSEID_FRMAE_START
* @retval none
*/
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid)
{
DVP->actrl_bit.hseid = dvp_hseid;
DVP->actrl_bit.vseid = dvp_vseid;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_edma.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the edma firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup EDMA
* @brief EDMA driver modules
* @{
*/
#ifdef EDMA_MODULE_ENABLED
/** @defgroup EDMA_private_functions
* @{
*/
/**
* @brief reset edma_streamx channely register.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @retval none.
*/
void edma_reset(edma_stream_type *edma_streamx)
{
/* reset registers for the selected stream */
edma_streamx->ctrl_bit.sen = FALSE;
edma_streamx->ctrl = 0x0;
edma_streamx->dtcnt = 0x0;
edma_streamx->paddr = 0x0;
edma_streamx->m0addr = 0x0;
edma_streamx->m1addr = 0x0;
edma_streamx->fctrl = (uint32_t)0x00000021;
/* reset interrupt pending bits for the selected stream */
switch((uint32_t)edma_streamx)
{
case EDMA_STREAM1_BASE:
EDMA->clr1 = EDMA_STREAM1_INT_MASK;
break;
case EDMA_STREAM2_BASE:
EDMA->clr1 = EDMA_STREAM2_INT_MASK;
break;
case EDMA_STREAM3_BASE:
EDMA->clr1 = EDMA_STREAM3_INT_MASK;
break;
case EDMA_STREAM4_BASE:
EDMA->clr1 = EDMA_STREAM4_INT_MASK;
break;
case EDMA_STREAM5_BASE:
EDMA->clr2 = EDMA_STREAM5_INT_MASK;
break;
case EDMA_STREAM6_BASE:
EDMA->clr2 = EDMA_STREAM6_INT_MASK;
break;
case EDMA_STREAM7_BASE:
EDMA->clr2 = EDMA_STREAM7_INT_MASK;
break;
case EDMA_STREAM8_BASE:
EDMA->clr2 = EDMA_STREAM8_INT_MASK;
break;
default: break;
}
}
/**
* @brief edma init.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param edma_init_struct: pointer to a edma_init_type structure.
* @retval none.
*/
void edma_init(edma_stream_type *edma_streamx, edma_init_type *edma_init_struct)
{
/* config dtd bits */
edma_streamx->ctrl_bit.dtd = edma_init_struct->direction;
/* config pincm bit */
edma_streamx->ctrl_bit.pincm = edma_init_struct->peripheral_inc_enable;
/* config mincm bit*/
edma_streamx->ctrl_bit.mincm = edma_init_struct->memory_inc_enable;
/* config pwidth bits */
edma_streamx->ctrl_bit.pwidth = edma_init_struct->peripheral_data_width;
/* config mwidth bits */
edma_streamx->ctrl_bit.mwidth = edma_init_struct->memory_data_width;
/* config lm bit */
edma_streamx->ctrl_bit.lm = edma_init_struct->loop_mode_enable;
/* config spl bits */
edma_streamx->ctrl_bit.spl = edma_init_struct->priority;
/* config mct bits */
edma_streamx->ctrl_bit.mct = edma_init_struct->memory_burst_mode;
/* config pct bits */
edma_streamx->ctrl_bit.pct = edma_init_struct->peripheral_burst_mode;
/* config fen bits */
edma_streamx->fctrl_bit.fen = edma_init_struct->fifo_mode_enable;
/* config fthsel bits*/
edma_streamx->fctrl_bit.fthsel = edma_init_struct->fifo_threshold;
/* config dtcnt */
edma_streamx->dtcnt = edma_init_struct->buffer_size;
/* config paddr */
edma_streamx->paddr = edma_init_struct->peripheral_base_addr;
/* config m0addr */
edma_streamx->m0addr = edma_init_struct->memory0_base_addr;
}
/**
* @brief edma init struct config with its default value.
* @param edma_init_struct: pointer to a edma_init_type structure which will be initialized.
* @retval none.
*/
void edma_default_para_init(edma_init_type *edma_init_struct)
{
edma_init_struct->buffer_size = 0;
edma_init_struct->loop_mode_enable = FALSE;
edma_init_struct->direction = EDMA_DIR_PERIPHERAL_TO_MEMORY;
edma_init_struct->fifo_threshold = EDMA_FIFO_THRESHOLD_1QUARTER;
edma_init_struct->fifo_mode_enable = FALSE;
edma_init_struct->memory0_base_addr = 0;
edma_init_struct->memory_burst_mode = EDMA_MEMORY_SINGLE;
edma_init_struct->memory_data_width = EDMA_MEMORY_DATA_WIDTH_BYTE;
edma_init_struct->memory_inc_enable = FALSE;
edma_init_struct->peripheral_base_addr = 0;
edma_init_struct->peripheral_burst_mode = EDMA_PERIPHERAL_SINGLE;
edma_init_struct->peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_BYTE;
edma_init_struct->peripheral_inc_enable = FALSE;
edma_init_struct->priority = EDMA_PRIORITY_LOW;
}
/**
* @brief enable or disable the edma streamx.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_stream_enable(edma_stream_type *edma_streamx, confirm_state new_state)
{
edma_streamx->ctrl_bit.sen = new_state;
}
/**
* @brief enable or disable the edma streamx interrupts.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param edma_int:
* this parameter can be one of the following values:
* - EDMA_FDT_INT
* - EDMA_HDT_INT
* - EDMA_DTERR_INT
* - EDMA_DMERR_INT
* - EDMA_FERR_INT
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_interrupt_enable(edma_stream_type *edma_streamx, uint32_t edma_int, confirm_state new_state)
{
if((edma_int & EDMA_FERR_INT) != 0)
{
if(new_state != FALSE)
{
edma_streamx->fctrl |= (uint32_t)EDMA_FERR_INT;
}
else
{
edma_streamx->fctrl &= ~(uint32_t)EDMA_FERR_INT;
}
}
if(edma_int != EDMA_FERR_INT)
{
if(new_state != FALSE)
{
edma_streamx->ctrl |= (uint32_t)edma_int;
}
else
{
edma_streamx->ctrl &= ~(uint32_t)edma_int;
}
}
}
/**
* @brief config the edma peripheral increment offset size mode.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param offset: peripheral increment offset size.
* this parameter can be one of the following values:
* - EDMA_PERIPHERAL_INC_PSIZE
* - EDMA_PERIPHERAL_INC_4_BYTE
* @retval none.
*/
void edma_peripheral_inc_offset_set(edma_stream_type *edma_streamx, edma_peripheral_inc_offset_type offset)
{
edma_streamx->ctrl_bit.pincos = offset;
}
/**
* @brief enable or disable the edma streamx flow controller.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_flow_controller_enable(edma_stream_type *edma_streamx, confirm_state new_state)
{
edma_streamx->ctrl_bit.pfctrl = new_state;
}
/**
* @brief set the number of data to be transferred.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param data_number: the number of data to be transferred (0x0000~0xFFFF).
* @retval none.
*/
void edma_data_number_set(edma_stream_type *edma_streamx, uint16_t data_number)
{
/* write the number of data units to be transferred */
edma_streamx->dtcnt = data_number;
}
/**
* @brief get the number of data to be transferred.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @retval the number value.
*/
uint16_t edma_data_number_get(edma_stream_type *edma_streamx)
{
return ((uint16_t)(edma_streamx->dtcnt));
}
/**
* @brief config the the double buffer mode.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param memory1_addr: the address of the second buffer.
* @param current_memory: specifies the target area of the first transfer.
* this parameter can be one of the following values:
* - EDMA_MEMORY_0
* - EDMA_MEMORY_1
* @retval none.
*/
void edma_double_buffer_mode_init(edma_stream_type *edma_streamx, uint32_t memory1_addr, edma_memory_type current_memory)
{
if(current_memory != EDMA_MEMORY_0)
{
edma_streamx->ctrl_bit.cm = 1;
}
else
{
edma_streamx->ctrl_bit.cm = 0;
}
edma_streamx->m1addr = memory1_addr;
}
/**
* @brief enable or disable the double memory mode.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_double_buffer_mode_enable(edma_stream_type *edma_streamx, confirm_state new_state)
{
if(new_state != FALSE)
{
edma_streamx->ctrl_bit.dmm = 1;
}
else
{
edma_streamx->ctrl_bit.dmm = 0;
}
}
/**
* @brief config the memory address in double buffer mode.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @param memory_addr: the address of the buffer.
* @param memory_target: indicates the which memory addr register will be config.
* this parameter can be one of the following values:
* - EDMA_MEMORY_0
* - EDMA_MEMORY_1
* @retval none.
*/
void edma_memory_addr_set(edma_stream_type *edma_streamx, uint32_t memory_addr, uint32_t memory_target)
{
if(memory_target != EDMA_MEMORY_0)
{
edma_streamx->m1addr = memory_addr;
}
else
{
edma_streamx->m0addr = memory_addr;
}
}
/**
* @brief get the current memory target.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @retval the memory target
* - EDMA_MEMORY_0
* - EDMA_MEMORY_1
*/
edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx)
{
return (edma_memory_type)(edma_streamx->ctrl_bit.cm);
}
/**
* @brief get the enable status of edma streamx.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @retval current state of the edma streamx (SET or RESET).
*/
flag_status edma_stream_status_get(edma_stream_type *edma_streamx)
{
if((edma_streamx->ctrl_bit.sen) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief get the fifo level status.
* @param edma_streamx:
* this parameter can be one of the following values:
* - EDMA_STREAM1
* - EDMA_STREAM2
* - EDMA_STREAM3
* - EDMA_STREAM4
* - EDMA_STREAM5
* - EDMA_STREAM6
* - EDMA_STREAM7
* - EDMA_STREAM8
* @retval the fifo filling state.
* - EDMA_FIFO_STATUS_LESS_1QUARTER: (0) < fifo level < (1/4).
* - EDMA_FIFO_STATUS_1QUARTER: (1/4) <= fifo level < (1/2) .
* - EDMA_FIFO_STATUS_HALF: (1/2) <= fifo level < (3/4).
* - EDMA_FIFO_STATUS_3QUARTER: (3/4) <= fifo level < (1).
* - EDMA_FIFO_STATUS_EMPTY: fifo is empty.
* - EDMA_FIFO_STATUS_FULL: fifo is full.
*/
uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx)
{
return (uint8_t)(edma_streamx->fctrl_bit.fsts);
}
/**
* @brief get the edma flag.
* @param edma_flag:
* this parameter can be one of the following values:
* - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG
* - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG
* - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG
* - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG
* - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG
* - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG
* - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG
* - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG
* @retval the new state of edma flag (SET or RESET).
*/
flag_status edma_flag_get(uint32_t edma_flag)
{
uint32_t status;
if(edma_flag > ((uint32_t)0x20000000))
{
status = EDMA->sts2;
}
else
{
status = EDMA->sts1;
}
if((status & edma_flag) != ((uint32_t)RESET))
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear the edma flag.
* @param edma_flag:
* this parameter can be one of the following values:
* - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG
* - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG
* - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG
* - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG
* - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG
* - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG
* - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG
* - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG
* @retval none.
*/
void edma_flag_clear(uint32_t edma_flag)
{
if(edma_flag > ((uint32_t)0x20000000))
{
EDMA->clr2 = (uint32_t)(edma_flag & 0x0FFFFFFF);
}
else
{
EDMA->clr1 = edma_flag;
}
}
/**
* @brief initialize the edma 2d mode.
* @param edma_streamx_2d:
* this parameter can be one of the following values:
* - EDMA_STREAM1_2D
* - EDMA_STREAM2_2D
* - EDMA_STREAM3_2D
* - EDMA_STREAM4_2D
* - EDMA_STREAM5_2D
* - EDMA_STREAM6_2D
* - EDMA_STREAM7_2D
* - EDMA_STREAM8_2D
* @param src_stride: source stride(-32768 ~ 32767).
* @param dst_stride: destination stride(-32768 ~ 32767).
* @param xcnt: x dimension transfer count(0x0000~ 0xFFFF).
* @param ycnt: y dimension transfer count(0x0000~ 0xFFFF).
* @retval none.
*/
void edma_2d_init(edma_stream_2d_type *edma_streamx_2d, int16_t src_stride, int16_t dst_stride, uint16_t xcnt, uint16_t ycnt)
{
edma_streamx_2d->s2dcnt = (uint32_t)((ycnt << 16) | (xcnt));
edma_streamx_2d->stride = (uint32_t)((dst_stride << 16) | (src_stride));
}
/**
* @brief enable or disable the edma 2d mode.
* @param edma_streamx_2d:
* this parameter can be one of the following values:
* - EDMA_STREAM1_2D
* - EDMA_STREAM2_2D
* - EDMA_STREAM3_2D
* - EDMA_STREAM4_2D
* - EDMA_STREAM5_2D
* - EDMA_STREAM6_2D
* - EDMA_STREAM7_2D
* - EDMA_STREAM8_2D
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_2d_enable(edma_stream_2d_type *edma_streamx_2d, confirm_state new_state)
{
uint32_t offset;
offset = ((uint32_t)edma_streamx_2d - EDMA_STREAM1_2D_BASE) / 4;
if(new_state != FALSE)
{
EDMA->s2dctrl |= (uint16_t)0x0001 << offset;
}
else
{
EDMA->s2dctrl &= ~((uint16_t)0x0001 << offset);
}
}
/**
* @brief initialize the edma link list.
* @param edma_streamx_ll:
* this parameter can be one of the following values:
* - EDMA_STREAM1_LL
* - EDMA_STREAM2_LL
* - EDMA_STREAM3_LL
* - EDMA_STREAM4_LL
* - EDMA_STREAM5_LL
* - EDMA_STREAM6_LL
* - EDMA_STREAM7_LL
* - EDMA_STREAM8_LL
* @param pointer: link list pointer.
* @retval none.
*/
void edma_link_list_init(edma_stream_link_list_type *edma_streamx_ll, uint32_t pointer)
{
edma_streamx_ll->llp = pointer;
}
/**
* @brief enable or disable the edma stream link list mode.
* @param edma_streamx_ll:
* this parameter can be any combination of the following values:
* - EDMA_STREAM1_LL
* - EDMA_STREAM2_LL
* - EDMA_STREAM3_LL
* - EDMA_STREAM4_LL
* - EDMA_STREAM5_LL
* - EDMA_STREAM6_LL
* - EDMA_STREAM7_LL
* - EDMA_STREAM8_LL
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edma_link_list_enable(edma_stream_link_list_type *edma_streamx_ll, confirm_state new_state)
{
uint32_t offset;
offset = ((uint32_t)edma_streamx_ll - EDMA_STREAM1_LL_BASE) / 4;
if(new_state != FALSE)
{
EDMA->llctrl |= (uint16_t)0x0001 << offset;
}
else
{
EDMA->llctrl &= ~((uint16_t)0x0001 << offset);
}
}
/**
* @brief enable or disable the edma edmamux.
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edmamux_enable(confirm_state new_state)
{
EDMA->muxsel_bit.tblsel = new_state;
}
/**
* @brief edmamux init.
* @param edmamux_channelx:
* this parameter can be one of the following values:
* - EDMAMUX_CHANNEL1
* - EDMAMUX_CHANNEL2
* - EDMAMUX_CHANNEL3
* - EDMAMUX_CHANNEL4
* - EDMAMUX_CHANNEL5
* - EDMAMUX_CHANNEL6
* - EDMAMUX_CHANNEL7
* - EDMAMUX_CHANNEL8
* @param edmamux_req_id:
* this parameter can be one of the following values:
* - EDMAMUX_DMAREQ_ID_REQ_G1 - EDMAMUX_DMAREQ_ID_REQ_G2 - EDMAMUX_DMAREQ_ID_REQ_G3 - EDMAMUX_DMAREQ_ID_REQ_G4
* - EDMAMUX_DMAREQ_ID_ADC1 - EDMAMUX_DMAREQ_ID_ADC2 - EDMAMUX_DMAREQ_ID_ADC3 - EDMAMUX_DMAREQ_ID_DAC1
* - EDMAMUX_DMAREQ_ID_DAC2 - EDMAMUX_DMAREQ_ID_TMR6_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR7_OVERFLOW- EDMAMUX_DMAREQ_ID_SPI1_RX
* - EDMAMUX_DMAREQ_ID_SPI1_TX - EDMAMUX_DMAREQ_ID_SPI2_RX - EDMAMUX_DMAREQ_ID_SPI2_TX - EDMAMUX_DMAREQ_ID_SPI3_RX
* - EDMAMUX_DMAREQ_ID_SPI3_TX - EDMAMUX_DMAREQ_ID_SPI4_RX - EDMAMUX_DMAREQ_ID_SPI4_TX - EDMAMUX_DMAREQ_ID_I2S2_EXT_RX
* - EDMAMUX_DMAREQ_ID_I2S2_EXT_TX - EDMAMUX_DMAREQ_ID_I2S3_EXT_RX - EDMAMUX_DMAREQ_ID_I2S3_EXT_TX - EDMAMUX_DMAREQ_ID_I2C1_RX
* - EDMAMUX_DMAREQ_ID_I2C1_TX - EDMAMUX_DMAREQ_ID_I2C2_RX - EDMAMUX_DMAREQ_ID_I2C2_TX - EDMAMUX_DMAREQ_ID_I2C3_RX
* - EDMAMUX_DMAREQ_ID_I2C3_TX - EDMAMUX_DMAREQ_ID_USART1_RX - EDMAMUX_DMAREQ_ID_USART1_TX - EDMAMUX_DMAREQ_ID_USART2_RX
* - EDMAMUX_DMAREQ_ID_USART2_TX - EDMAMUX_DMAREQ_ID_USART3_RX - EDMAMUX_DMAREQ_ID_USART3_TX - EDMAMUX_DMAREQ_ID_UART4_RX
* - EDMAMUX_DMAREQ_ID_UART4_TX - EDMAMUX_DMAREQ_ID_UART5_RX - EDMAMUX_DMAREQ_ID_UART5_TX - EDMAMUX_DMAREQ_ID_USART6_RX
* - EDMAMUX_DMAREQ_ID_USART6_TX - EDMAMUX_DMAREQ_ID_UART7_RX - EDMAMUX_DMAREQ_ID_UART7_TX - EDMAMUX_DMAREQ_ID_UART8_RX
* - EDMAMUX_DMAREQ_ID_UART8_TX - EDMAMUX_DMAREQ_ID_SDIO1 - EDMAMUX_DMAREQ_ID_SDIO2 - EDMAMUX_DMAREQ_ID_QSPI1
* - EDMAMUX_DMAREQ_ID_QSPI2 - EDMAMUX_DMAREQ_ID_TMR1_CH1 - EDMAMUX_DMAREQ_ID_TMR1_CH2 - EDMAMUX_DMAREQ_ID_TMR1_CH3
* - EDMAMUX_DMAREQ_ID_TMR1_CH4 - EDMAMUX_DMAREQ_ID_TMR1_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR1_TRIG - EDMAMUX_DMAREQ_ID_TMR1_COM
* - EDMAMUX_DMAREQ_ID_TMR8_CH1 - EDMAMUX_DMAREQ_ID_TMR8_CH2 - EDMAMUX_DMAREQ_ID_TMR8_CH3 - EDMAMUX_DMAREQ_ID_TMR8_CH4
* - EDMAMUX_DMAREQ_ID_TMR8_UP - EDMAMUX_DMAREQ_ID_TMR8_TRIG - EDMAMUX_DMAREQ_ID_TMR8_COM - EDMAMUX_DMAREQ_ID_TMR2_CH1
* - EDMAMUX_DMAREQ_ID_TMR2_CH2 - EDMAMUX_DMAREQ_ID_TMR2_CH3 - EDMAMUX_DMAREQ_ID_TMR2_CH4 - EDMAMUX_DMAREQ_ID_TMR2_OVERFLOW
* - EDMAMUX_DMAREQ_ID_TMR2_TRIG - EDMAMUX_DMAREQ_ID_TMR3_CH1 - EDMAMUX_DMAREQ_ID_TMR3_CH2 - EDMAMUX_DMAREQ_ID_TMR3_CH3
* - EDMAMUX_DMAREQ_ID_TMR3_CH4 - EDMAMUX_DMAREQ_ID_TMR3_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR3_TRIG - EDMAMUX_DMAREQ_ID_TMR4_CH1
* - EDMAMUX_DMAREQ_ID_TMR4_CH2 - EDMAMUX_DMAREQ_ID_TMR4_CH3 - EDMAMUX_DMAREQ_ID_TMR4_CH4 - EDMAMUX_DMAREQ_ID_TMR4_OVERFLOW
* - EDMAMUX_DMAREQ_ID_TMR4_TRIG - EDMAMUX_DMAREQ_ID_TMR5_CH1 - EDMAMUX_DMAREQ_ID_TMR5_CH2 - EDMAMUX_DMAREQ_ID_TMR5_CH3
* - EDMAMUX_DMAREQ_ID_TMR5_CH4 - EDMAMUX_DMAREQ_ID_TMR5_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR5_TRIG - EDMAMUX_DMAREQ_ID_TMR20_CH1
* - EDMAMUX_DMAREQ_ID_TMR20_CH2 - EDMAMUX_DMAREQ_ID_TMR20_CH3 - EDMAMUX_DMAREQ_ID_TMR20_CH4 - EDMAMUX_DMAREQ_ID_TMR20_OVERFLOW
* - EDMAMUX_DMAREQ_ID_TMR20_TRIG - EDMAMUX_DMAREQ_ID_TMR20_HALL - EDMAMUX_DMAREQ_ID_DVP
* @retval none.
*/
void edmamux_init(edmamux_channel_type *edmamux_channelx, edmamux_requst_id_sel_type edmamux_req_id)
{
edmamux_channelx->muxctrl_bit.reqsel = edmamux_req_id;
}
/**
* @brief edmamux sync init struct config with its default value.
* @param edmamux_sync_init_struct: pointer to a edmamux_sync_init_type structure which will be initialized.
* @retval none.
*/
void edmamux_sync_default_para_init(edmamux_sync_init_type *edmamux_sync_init_struct)
{
edmamux_sync_init_struct->sync_enable = FALSE;
edmamux_sync_init_struct->sync_event_enable = FALSE;
edmamux_sync_init_struct->sync_polarity = EDMAMUX_SYNC_POLARITY_DISABLE;
edmamux_sync_init_struct->sync_request_number = 0x0;
edmamux_sync_init_struct->sync_signal_sel = EDMAMUX_SYNC_ID_EXINT0;
}
/**
* @brief edmamux synchronization config.
* @param edmamux_channelx:
* this parameter can be one of the following values:
* - EDMAMUX_CHANNEL1
* - EDMAMUX_CHANNEL2
* - EDMAMUX_CHANNEL3
* - EDMAMUX_CHANNEL4
* - EDMAMUX_CHANNEL5
* - EDMAMUX_CHANNEL6
* - EDMAMUX_CHANNEL7
* - EDMAMUX_CHANNEL8
* @param edmamux_sync_init_struct: ointer to a edmamux_sync_init_type structure.
* @retval none.
*/
void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_init_type *edmamux_sync_init_struct)
{
edmamux_channelx->muxctrl_bit.syncsel = edmamux_sync_init_struct->sync_signal_sel;
edmamux_channelx->muxctrl_bit.syncpol = edmamux_sync_init_struct->sync_polarity;
edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number;
edmamux_channelx->muxctrl_bit.evtgen = edmamux_sync_init_struct->sync_event_enable;
edmamux_channelx->muxctrl_bit.syncen = edmamux_sync_init_struct->sync_enable;
}
/**
* @brief edmamux request generator init struct config with its default value.
* @param edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
* @retval none.
*/
void edmamux_generator_default_para_init(edmamux_gen_init_type *edmamux_gen_init_struct)
{
edmamux_gen_init_struct->gen_enable = FALSE;
edmamux_gen_init_struct->gen_polarity = EDMAMUX_GEN_POLARITY_DISABLE;
edmamux_gen_init_struct->gen_request_number = 0x0;
edmamux_gen_init_struct->gen_signal_sel = EDMAMUX_GEN_ID_EXINT0;
}
/**
* @brief edmamux request generator init.
* @param edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
* @retval none.
*/
void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen_init_type *edmamux_gen_init_struct)
{
edmamux_gen_x->gctrl_bit.sigsel = edmamux_gen_init_struct->gen_signal_sel;
edmamux_gen_x->gctrl_bit.gpol = edmamux_gen_init_struct->gen_polarity;
edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number;
edmamux_gen_x->gctrl_bit.gen = edmamux_gen_init_struct->gen_enable;
}
/**
* @brief enable or disable the edmamux sync interrupts.
* @param edmamux_channelx:
* this parameter can be one of the following values:
* - EDMAMUX_CHANNEL1
* - EDMAMUX_CHANNEL2
* - EDMAMUX_CHANNEL3
* - EDMAMUX_CHANNEL4
* - EDMAMUX_CHANNEL5
* - EDMAMUX_CHANNEL6
* - EDMAMUX_CHANNEL7
* - EDMAMUX_CHANNEL8
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state)
{
if(new_state != FALSE)
{
edmamux_channelx->muxctrl_bit.syncovien = TRUE;
}
else
{
edmamux_channelx->muxctrl_bit.syncovien = FALSE;
}
}
/**
* @brief enable or disable the edmamux request generator interrupts.
* @param edmamux_gen_x: pointer to a edmamux_generator_type structure.
* this parameter can be one of the following values:
* - EDMAMUX_GENERATOR1
* - EDMAMUX_GENERATOR2
* - EDMAMUX_GENERATOR3
* - EDMAMUX_GENERATOR4
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state)
{
if(new_state != FALSE)
{
edmamux_gen_x->gctrl_bit.trgovien = TRUE;
}
else
{
edmamux_gen_x->gctrl_bit.trgovien = FALSE;
}
}
/**
* @brief edmamux sync flag get.
* @param flag
* this parameter can be any combination of the following values:
* - EDMAMUX_SYNC_OV1_FLAG
* - EDMAMUX_SYNC_OV2_FLAG
* - EDMAMUX_SYNC_OV3_FLAG
* - EDMAMUX_SYNC_OV4_FLAG
* - EDMAMUX_SYNC_OV5_FLAG
* - EDMAMUX_SYNC_OV6_FLAG
* - EDMAMUX_SYNC_OV7_FLAG
* - EDMAMUX_SYNC_OV8_FLAG
* @retval state of edmamux sync flag.
*/
flag_status edmamux_sync_flag_get(uint32_t flag)
{
if((EDMA->muxsyncsts & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief edmamux sync flag clear.
* @param flag
* this parameter can be any combination of the following values:
* - EDMAMUX_SYNC_OV1_FLAG
* - EDMAMUX_SYNC_OV2_FLAG
* - EDMAMUX_SYNC_OV3_FLAG
* - EDMAMUX_SYNC_OV4_FLAG
* - EDMAMUX_SYNC_OV5_FLAG
* - EDMAMUX_SYNC_OV6_FLAG
* - EDMAMUX_SYNC_OV7_FLAG
* - EDMAMUX_SYNC_OV8_FLAG
* @retval none.
*/
void edmamux_sync_flag_clear(uint32_t flag)
{
EDMA->muxsyncclr = flag;
}
/**
* @brief edmamux request generator flag get.
* @param flag
* this parameter can be any combination of the following values:
* - EDMAMUX_GEN_TRIG_OV1_FLAG
* - EDMAMUX_GEN_TRIG_OV2_FLAG
* - EDMAMUX_GEN_TRIG_OV3_FLAG
* - EDMAMUX_GEN_TRIG_OV4_FLAG
* @retval state of edmamux sync flag.
*/
flag_status edmamux_generator_flag_get(uint32_t flag)
{
if((EDMA->muxgsts & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief edmamux request generator flag clear.
* @param flag
* this parameter can be any combination of the following values:
* - EDMAMUX_GEN_TRIG_OV1_FLAG
* - EDMAMUX_GEN_TRIG_OV2_FLAG
* - EDMAMUX_GEN_TRIG_OV3_FLAG
* - EDMAMUX_GEN_TRIG_OV4_FLAG
* @retval none.
*/
void edmamux_generator_flag_clear(uint32_t flag)
{
EDMA->muxgclr = flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_exint.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup EXINT
* @brief EXINT driver modules
* @{
*/
#ifdef EXINT_MODULE_ENABLED
/** @defgroup EXINT_private_functions
* @{
*/
/**
* @brief exint reset
* @param none
* @retval none
*/
void exint_reset(void)
{
EXINT->inten = 0x00000000;
EXINT->polcfg1 = 0x00000000;
EXINT->polcfg2 = 0x00000000;
EXINT->evten = 0x00000000;
EXINT->intsts = 0x007FFFFF;
}
/**
* @brief exint default para init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_default_para_init(exint_init_type *exint_struct)
{
exint_struct->line_enable = FALSE;
exint_struct->line_select = EXINT_LINE_NONE;
exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
exint_struct->line_mode = EXINT_LINE_EVENT;
}
/**
* @brief exint init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_init(exint_init_type *exint_struct)
{
uint32_t line_index = 0;
line_index = exint_struct->line_select;
EXINT->inten &= ~line_index;
EXINT->evten &= ~line_index;
if(exint_struct->line_enable != FALSE)
{
if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
{
EXINT->inten |= line_index;
}
else
{
EXINT->evten |= line_index;
}
EXINT->polcfg1 &= ~line_index;
EXINT->polcfg2 &= ~line_index;
if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
{
EXINT->polcfg1 |= line_index;
}
else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
{
EXINT->polcfg2 |= line_index;
}
else
{
EXINT->polcfg1 |= line_index;
EXINT->polcfg2 |= line_index;
}
}
}
/**
* @brief clear exint flag
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @retval none
*/
void exint_flag_clear(uint32_t exint_line)
{
EXINT->intsts = exint_line;
}
/**
* @brief get exint flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @retval the new state of exint flag(SET or RESET).
*/
flag_status exint_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief generate exint software interrupt event
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @retval none
*/
void exint_software_interrupt_event_generate(uint32_t exint_line)
{
EXINT->swtrg |= exint_line;
}
/**
* @brief enable or disable exint interrupt
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @param new_state: new state of exint interrupt.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->inten |= exint_line;
}
else
{
EXINT->inten &= ~exint_line;
}
}
/**
* @brief enable or disable exint event
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @param new_state: new state of exint event.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void exint_event_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->evten |= exint_line;
}
else
{
EXINT->evten &= ~exint_line;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_gpio.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
#ifdef GPIO_MODULE_ENABLED
/** @defgroup GPIO_private_functions
* @{
*/
/**
* @brief reset the gpio register
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @retval none
*/
void gpio_reset(gpio_type *gpio_x)
{
if(gpio_x == GPIOA)
{
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOB)
{
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOC)
{
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOD)
{
crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOE)
{
crm_periph_reset(CRM_GPIOE_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOE_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOF)
{
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOG)
{
crm_periph_reset(CRM_GPIOG_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOG_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOH)
{
crm_periph_reset(CRM_GPIOH_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOH_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the gpio peripheral.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param gpio_init_struct: pointer to gpio init structure.
* @retval none
*/
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
{
uint16_t pinx_value, pin_index = 0;
pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
while(pinx_value > 0)
{
if(pinx_value & 0x01)
{
gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
}
pinx_value >>= 1;
pin_index++;
}
}
/**
* @brief fill each gpio_init_type member with its default value.
* @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
* @retval none
*/
void gpio_default_para_init(gpio_init_type *gpio_init_struct)
{
/* reset gpio init structure parameters values */
gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
}
/**
* @brief read the specified input port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if(pins != (pins & gpio_x->idt))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief read the specified gpio input data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @retval gpio input data port value.
*/
uint16_t gpio_input_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->idt));
}
/**
* @brief read the specified output port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if((gpio_x->odt & pins) != RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief read the specified gpio ouput data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @retval gpio input data port value.
*/
uint16_t gpio_output_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->odt));
}
/**
* @brief set the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->scr = pins;
}
/**
* @brief clear the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->clr = pins;
}
/**
* @brief set or clear the selected data port bit.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
* @retval none
*/
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
{
if(bit_state != FALSE)
{
gpio_x->scr = pins;
}
else
{
gpio_x->clr = pins;
}
}
/**
* @brief write data to the specified gpio data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param port_value: specifies the value to be written to the port output data register.
* @retval none
*/
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
{
gpio_x->odt = port_value;
}
/**
* @brief write protect gpio pins configuration registers.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* this parameter can be any combination of the following:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
{
uint32_t temp = 0x00010000;
temp |= pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* reset wpen bit */
gpio_x->wpr = pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* read wpen bit*/
temp = gpio_x->wpr;
/* read wpen bit*/
temp = gpio_x->wpr;
}
/**
* @brief enable or disable gpio pins huge driven.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param new_state: new state of the slew rate.
* this parameter can be: true or false.
* @retval none
*/
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
{
if(new_state != FALSE)
{
gpio_x->hdrv |= pins;
}
else
{
gpio_x->hdrv &= ~pins;
}
}
/**
* @brief configure the pin's muxing function.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
* @param gpio_pin_source: specifies the pin for the muxing function.
* this parameter can be one of the following values:
* - GPIO_PINS_SOURCE0
* - GPIO_PINS_SOURCE1
* - GPIO_PINS_SOURCE2
* - GPIO_PINS_SOURCE3
* - GPIO_PINS_SOURCE4
* - GPIO_PINS_SOURCE5
* - GPIO_PINS_SOURCE6
* - GPIO_PINS_SOURCE7
* - GPIO_PINS_SOURCE8
* - GPIO_PINS_SOURCE9
* - GPIO_PINS_SOURCE10
* - GPIO_PINS_SOURCE11
* - GPIO_PINS_SOURCE12
* - GPIO_PINS_SOURCE13
* - GPIO_PINS_SOURCE14
* - GPIO_PINS_SOURCE15
* @param gpio_mux: select the pin to used as muxing function.
* this parameter can be one of the following values:
* - GPIO_MUX_0
* - GPIO_MUX_1
* - GPIO_MUX_2
* - GPIO_MUX_3
* - GPIO_MUX_4
* - GPIO_MUX_5
* - GPIO_MUX_6
* - GPIO_MUX_7
* - GPIO_MUX_8
* - GPIO_MUX_9
* - GPIO_MUX_10
* - GPIO_MUX_11
* - GPIO_MUX_12
* - GPIO_MUX_13
* - GPIO_MUX_14
* - GPIO_MUX_15
* @retval none
*/
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
if(gpio_pin_source >> 0x03)
{
gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxh | temp;
gpio_x->muxh = temp_2;
}
else
{
gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxl | temp;
gpio_x->muxl = temp_2;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_i2c.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup I2C
* @brief I2C driver modules
* @{
*/
#ifdef I2C_MODULE_ENABLED
/** @defgroup I2C_private_functions
* @{
*/
/**
* @brief reset the i2c register
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval none
*/
void i2c_reset(i2c_type *i2c_x)
{
if(i2c_x == I2C1)
{
crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
}
else if(i2c_x == I2C2)
{
crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
}
else if(i2c_x == I2C3)
{
crm_periph_reset(CRM_I2C3_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C3_PERIPH_RESET, FALSE);
}
}
/**
* @brief init i2c digit filters and clock control register.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param dfilters: number of digit filters (0x00~0x0F).
* @param clk: i2c clock control register (0x00000000~0xFFFFFFFF).
* @retval none
*/
void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk)
{
/* disable i2c peripheral */
i2c_x->ctrl1_bit.i2cen = FALSE;
/* write clkctrl register*/
i2c_x->clkctrl = clk;
/* write digital filter register*/
i2c_x->ctrl1_bit.dflt = dfilters;
}
/**
* @brief config i2c own address 1.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param mode: i2c address mode.
* this parameter can be one of the following values:
* - I2C_ADDRESS_MODE_7BIT: 7bit address.
* - I2C_ADDRESS_MODE_10BIT: 10bit address.
* @param address: own address 1, such as 0xB0.
* @retval none
*/
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
{
/* config address mode */
i2c_x->oaddr1_bit.addr1mode = mode;
/* config address */
i2c_x->oaddr1_bit.addr1 = address & 0x03FF;
/* enable address */
i2c_x->oaddr1_bit.addr1en = TRUE;
}
/**
* @brief config i2c own address 2 and mask.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param address: own address 1, such as 0xC0.
* @param mask: own address 2 mask.
* this parameter can be one of the following values:
* - I2C_ADDR2_NOMASK: compare bit [7:1].
* - I2C_ADDR2_MASK01: only compare bit [7:2].
* - I2C_ADDR2_MASK02: only compare bit [7:2].
* - I2C_ADDR2_MASK03: only compare bit [7:3].
* - I2C_ADDR2_MASK04: only compare bit [7:4].
* - I2C_ADDR2_MASK05: only compare bit [7:5].
* - I2C_ADDR2_MASK06: only compare bit [7:6].
* - I2C_ADDR2_MASK07: only compare bit [7].
* @retval none
*/
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
{
i2c_x->oaddr2_bit.addr2mask = mask;
i2c_x->oaddr2_bit.addr2 = (address >> 1) & 0x7F;
}
/**
* @brief enable or disable own address 2.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->oaddr2_bit.addr2en = new_state;
}
/**
* @brief enable or disable smbus mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param mode: smbus device mode.
* this parameter can be one of the following values:
* - I2C_SMBUS_MODE_DEVICE: smbus device.
* - I2C_SMBUS_MODE_HOST: smbus host.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state)
{
switch (mode)
{
case I2C_SMBUS_MODE_DEVICE:
i2c_x->ctrl1_bit.devaddren = new_state;
break;
case I2C_SMBUS_MODE_HOST:
i2c_x->ctrl1_bit.haddren = new_state;
break;
default:
break;
}
}
/**
* @brief enable or disable peripheral.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.i2cen = new_state;
}
/**
* @brief enable or disable clock stretch.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.stretch = (!new_state);
}
/**
* @brief enable or disable ack.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none.
*/
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.nacken = (!new_state);
}
/**
* @brief enable or disable 10-bit address mode (master transfer).
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.addr10 = new_state;
}
/**
* @brief config the slave address to be transmitted.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param address: slave address.
* @retval none
*/
void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address)
{
i2c_x->ctrl2_bit.saddr = address & 0x03FF;
}
/**
* @brief get the slave address to be transmitted.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval slave address
*/
uint16_t i2c_transfer_addr_get(i2c_type *i2c_x)
{
return i2c_x->ctrl2_bit.saddr;
}
/**
* @brief config the master transfer direction.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param i2c_direction: transfer request direction.
* this parameter can be one of the following values:
* - I2C_DIR_TRANSMIT: master request a write transfer.
* - I2C_DIR_RECEIVE: master request a read transfer.
* @retval none
*/
void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
{
i2c_x->ctrl2_bit.dir = i2c_direction;
}
/**
* @brief slave get the i2c transfer direction.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval the value of the slave direction
* - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode.
* - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode.
*/
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
{
if (i2c_x->sts_bit.sdir == 0)
{
return I2C_DIR_TRANSMIT;
}
else
{
return I2C_DIR_RECEIVE;
}
}
/**
* @brief get the i2c slave matched address.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval slave matched address.
*/
uint8_t i2c_matched_addr_get(i2c_type *i2c_x)
{
return (i2c_x->sts_bit.addr << 1);
}
/**
* @brief enable or disable auto send stop mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.astopen = new_state;
}
/**
* @brief enable or disable cnt reload mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.rlden = new_state;
}
/**
* @brief config the transfer cnt .
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param cnt: transfer cnt.
* @retval none
*/
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt)
{
i2c_x->ctrl2_bit.cnt = cnt;
}
/**
* @brief enable or disable read 10-bit header, this mode
* only used in 10-bit address mode read.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.readh10 = new_state;
}
/**
* @brief enable or disable general call mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.gcaen = new_state;
}
/**
* @brief drives the smbus alert pin high or low.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param level
* this parameter can be one of the following values:
* - I2C_SMBUS_ALERT_LOW: smbus alert set low.
* - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
* @retval none
*/
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
{
i2c_x->ctrl1_bit.smbalert = level;
}
/**
* @brief enable or disable slave data control.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.sctrl = new_state;
}
/**
* @brief enable or disable pec calculate.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.pecen = new_state;
}
/**
* @brief enable or disable pec transfer.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.pecten = new_state;
}
/**
* @brief get the i2c pec value.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval the value of the pec.
*/
uint8_t i2c_pec_value_get(i2c_type *i2c_x)
{
return (uint8_t)(i2c_x->pec_bit.pecval);
}
/**
* @brief config the i2c bus timeout.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param timeout: timeout (0x0000~0x0FFF).
* @retval none
*/
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout)
{
i2c_x->timeout_bit.totime = timeout;
}
/**
* @brief config the bus timeout detcet level.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param level
* this parameter can be one of the following values:
* - I2C_TIMEOUT_DETCET_HIGH: detect high level timeout.
* - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
* @retval none
*/
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode)
{
i2c_x->timeout_bit.tomode = mode;
}
/**
* @brief enable or disable bus timeout.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->timeout_bit.toen = new_state;
}
/**
* @brief config the i2c extend bus timeout.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param timeout: extend timeout (0x0000~0x0FFF).
* @retval none
*/
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout)
{
i2c_x->timeout_bit.exttime = timeout;
}
/**
* @brief enable or disable extend bus timeout.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->timeout_bit.exten = new_state;
}
/**
* @brief enable or disable interrupts.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param i2c_int: interrupts sources.
* this parameter can be one of the following values:
* - I2C_TD_INT: transmit data interrupt.
* - I2C_RD_INT: receive data interrupt.
* - I2C_ADDR_INT: address match interrupt.
* - I2C_ACKFIAL_INT: ack fail interrupt.
* - I2C_STOP_INT: stop detect interrupt.
* - I2C_TDC_INT: transmit data complete interrupt.
* - I2C_ERR_INT: bus error interrupt.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state)
{
if (new_state != FALSE)
{
i2c_x->ctrl1 |= source;
}
else
{
i2c_x->ctrl1 &= (uint32_t)~source;
}
}
/**
* @brief get interrupt status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param source
* this parameter can be one of the following values:
* - I2C_TD_INT: transmit data interrupt.
* - I2C_RD_INT: receive data interrupt.
* - I2C_ADDR_INT: address match interrupt.
* - I2C_ACKFIAL_INT: ack fail interrupt.
* - I2C_STOP_INT: stop detect interrupt.
* - I2C_TDC_INT: transmit data complete interrupt.
* - I2C_ERR_INT: bus error interrupt.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
{
if((i2c_x->ctrl1 & source) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief enable or disable dma requests.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param dma_req: dma transfer request.
* this parameter can be one of the following values:
* - I2C_DMA_REQUEST_TX: dma transmit request.
* - I2C_DMA_REQUEST_RX: dma receive request.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state)
{
if(dma_req == I2C_DMA_REQUEST_TX)
{
i2c_x->ctrl1_bit.dmaten = new_state;
}
else
{
i2c_x->ctrl1_bit.dmaren = new_state;
}
}
/**
* @brief config data transfer.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param address: slave address.
* @param cnt: transfer conuter(0~255)
* @param rld_stop: config reload and gen stop condition mode.
* this parameter can be one of the following values:
* - I2C_AUTO_STOP_MODE: auto generate stop mode.
* - I2C_SOFT_STOP_MODE: soft generate stop mode.
* - I2C_RELOAD_MODE: reload mode.
* @param start: config gen start condition mode.
* this parameter can be one of the following values:
* - I2C_WITHOUT_START: transfer data without start condition.
* - I2C_GEN_START_READ: read data and generate start.
* - I2C_GEN_START_WRITE: send data and generate start.
* @retval none
*/
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start)
{
uint32_t temp;
/* copy ctrl2 value to temp */
temp = i2c_x->ctrl2;
/* clear ctrl2_bit specific bits */
temp &= ~0x03FF67FF;
/* transfer mode and address set */
temp |= address | rld_stop | start;
/* transfer counter set */
temp |= (uint32_t)cnt << 16;
/* update ctrl2 value */
i2c_x->ctrl2 = temp;
}
/**
* @brief generate start condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval none
*/
void i2c_start_generate(i2c_type *i2c_x)
{
i2c_x->ctrl2_bit.genstart = TRUE;
}
/**
* @brief generate stop condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval none
*/
void i2c_stop_generate(i2c_type *i2c_x)
{
i2c_x->ctrl2_bit.genstop = TRUE;
}
/**
* @brief send a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param data: byte to be transmitted.
* @retval none
*/
void i2c_data_send(i2c_type *i2c_x, uint8_t data)
{
i2c_x->txdt = data;
}
/**
* @brief receive a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval the value of the received data.
*/
uint8_t i2c_data_receive(i2c_type *i2c_x)
{
return (uint8_t)i2c_x->rxdt;
}
/**
* @brief get flag status.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_TDIS_FLAG: send interrupt status.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_BUSYF_FLAG: bus busy flag transmission mode.
* - I2C_SDIR_FLAG: slave data transmit direction.
* @retval the new state of flag (SET or RESET).
*/
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
{
if((i2c_x->sts & flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param flag: specifies the flag to clear.
* this parameter can be any combination of the following values:
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* @retval none
*/
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
{
i2c_x->clr = flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_misc.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
#ifdef MISC_MODULE_ENABLED
/** @defgroup MISC_private_functions
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @brief system reset
* @param none
* @retval none
*/
void nvic_system_reset(void)
{
NVIC_SystemReset();
}
/**
* @brief enable nvic irq
* @param irqn (IRQn_Type number)
* @param preempt_priority: preemptive priority value (starting from 0)
* @param sub_priority: subpriority value (starting from 0)
* @retval none
*/
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
{
uint32_t temp_priority = 0;
/* encode priority */
temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
/* set priority */
NVIC_SetPriority(irqn, temp_priority);
/* enable irqn */
NVIC_EnableIRQ(irqn);
}
/**
* @brief disable nvic irq number
* @param irqn (IRQn_Type number)
* @retval none
*/
void nvic_irq_disable(IRQn_Type irqn)
{
NVIC_DisableIRQ(irqn);
}
/**
* @brief config nvic priority group
* @param priority_group
* this parameter can be one of the following values:
* - NVIC_PRIORITY_GROUP_0
* - NVIC_PRIORITY_GROUP_1
* - NVIC_PRIORITY_GROUP_2
* - NVIC_PRIORITY_GROUP_3
* - NVIC_PRIORITY_GROUP_4
* @retval none
*/
void nvic_priority_group_config(nvic_priority_group_type priority_group)
{
/* set the prigroup[10:8] bits according to nvic_prioritygroup value */
NVIC_SetPriorityGrouping(priority_group);
}
/**
* @brief set the vector table location and offset.
* @param base
* this parameter can be one of the following values:
* - NVIC_VECTTAB_RAM
* - NVIC_VECTTAB_FLASH
* @param offset (vector table base offset field. this value must be a multiple of 0x200)
* @retval none
*/
void nvic_vector_table_set(uint32_t base, uint32_t offset)
{
SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief config nvic lowpower mode
* @param lp_mode
* this parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
* @param new_state (new state of lp condition. ENABLE or DISABLE)
* @retval none
*/
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
SCB->SCR |= lp_mode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
}
}
/**
* @brief config systick clock source
* @param source
* this parameter can be one of the following values:
* - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
* - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
* @retval none
*/
void systick_clock_source_config(systick_clock_source_type source)
{
if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
{
SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
else
{
SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_pwc.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup PWC
* @brief PWC driver modules
* @{
*/
#ifdef PWC_MODULE_ENABLED
/** @defgroup PWC_private_functions
* @{
*/
/**
* @brief deinitialize the pwc peripheral registers to their default reset values.
* @param none
* @retval none
*/
void pwc_reset(void)
{
crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable access to the battery powered domain.
* @param new_state: new state of battery powered domain access.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_battery_powered_domain_access(confirm_state new_state)
{
PWC->ctrl_bit.bpwen= new_state;
}
/**
* @brief select the voltage threshold detected by the power voltage detector.
* @param pvm_voltage: select pwc pvm voltage
* this parameter can be one of the following values:
* - PWC_PVM_VOLTAGE_2V3
* - PWC_PVM_VOLTAGE_2V4
* - PWC_PVM_VOLTAGE_2V5
* - PWC_PVM_VOLTAGE_2V6
* - PWC_PVM_VOLTAGE_2V7
* - PWC_PVM_VOLTAGE_2V8
* - PWC_PVM_VOLTAGE_2V9
* @retval none
*/
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
{
PWC->ctrl_bit.pvmsel= pvm_voltage;
}
/**
* @brief enable or disable pwc power voltage monitor (pvm)
* @param new_state: new state of pvm.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_power_voltage_monitor_enable(confirm_state new_state)
{
PWC->ctrl_bit.pvmen= new_state;
}
/**
* @brief enable or disable pwc standby wakeup pin
* @param pin_num: choose the wakeup pin.
* this parameter can be be any combination of the following values:
* - PWC_WAKEUP_PIN_1
* - PWC_WAKEUP_PIN_2
* @param new_state: new state of the standby wakeup pin.
* this parameter can be one of the following values:
* - TRUE <wakeup pin is used for wake up cpu from standby mode>
* - FALSE <wakeup pin is used for general purpose I/O>
* @retval none
*/
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
{
if(new_state == TRUE)
{
PWC->ctrlsts |= pin_num;
}
else
{
PWC->ctrlsts &= ~pin_num;
}
}
/**
* @brief clear flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be any combination of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
* @retval none
*/
void pwc_flag_clear(uint32_t pwc_flag)
{
if(pwc_flag & PWC_STANDBY_FLAG)
PWC->ctrl_bit.clsef = TRUE;
if(pwc_flag & PWC_WAKEUP_FLAG)
PWC->ctrl_bit.clswef = TRUE;
}
/**
* @brief get flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be one of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - PWC_PVM_OUTPUT_FLAG
* @retval state of select flag(SET or RESET).
*/
flag_status pwc_flag_get(uint32_t pwc_flag)
{
flag_status status = RESET;
if ((PWC->ctrlsts & pwc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief enter pwc sleep mode
* @param sleep_mode_enter: choose the instruction to enter sleep mode.
* this parameter can be one of the following values:
* - PWC_SLEEP_ENTER_WFI
* - PWC_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
{
SCB->SCR &= (uint32_t)~0x4;
if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
{
__WFI();
}
}
/**
* @brief enter pwc deep-sleep mode
* @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
* this parameter can be one of the following values:
* - PWC_DEEP_SLEEP_ENTER_WFI
* - PWC_DEEP_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
{
SCB->SCR |= 0x04;
if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
{
__WFI();
}
SCB->SCR &= (uint32_t)~0x4;
}
/**
* @brief regulate low power consumption in the deep sleep mode
* @param pwc_regulator: set the regulator state.
* this parameter can be one of the following values:
* - PWC_REGULATOR_ON
* - PWC_REGULATOR_LOW_POWER
* @retval none
*/
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
{
PWC->ctrl_bit.vrsel = pwc_regulator;
}
/**
* @brief enter pwc standby mode
* @param none
* @retval none
*/
void pwc_standby_mode_enter(void)
{
PWC->ctrl_bit.clswef = TRUE;
PWC->ctrl_bit.lpsel = TRUE;
SCB->SCR |= 0x04;
#if defined (__CC_ARM)
__force_stores();
#endif
while(1)
{
__WFI();
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_qspi.c
* @version v2.1.0
* @date 2022-08-16
* @brief contain all the functions for qspi firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup QSPI
* @brief QSPI driver modules
* @{
*/
#ifdef QSPI_MODULE_ENABLED
/** @defgroup QSPI_private_functions
* @{
*/
/**
* @brief enable/disable encryption for qspi.
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
{
qspi_x->ctrl_bit.keyen = new_state;
}
/**
* @brief set qspi sck mode.
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_mode: new state to be set
* this parameter can be one of the following values:
* - QSPI_SCK_MODE_0
* - QSPI_SCK_MODE_3
* @retval none
*/
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode)
{
qspi_x->ctrl_bit.sckmode = new_mode;
}
/**
* @brief set qspi clock division
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_clkdiv: new division value
* this parameter can be one of the following values:
* - QSPI_CLK_DIV_2
* - QSPI_CLK_DIV_4
* - QSPI_CLK_DIV_6
* - QSPI_CLK_DIV_8
* - QSPI_CLK_DIV_3
* - QSPI_CLK_DIV_5
* - QSPI_CLK_DIV_10
* - QSPI_CLK_DIV_12
* @retval none
*/
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv)
{
qspi_x->ctrl_bit.clkdiv = new_clkdiv;
}
/**
* @brief enable/disable cache in xip mode
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state)
{
qspi_x->xip_cmd_w3_bit.bypassc = new_state;
}
/**
* @brief enable/disable interrupt when command is completed
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
{
qspi_x->ctrl2_bit.cmdie = new_state;
}
/**
* @brief get status flags.
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - QSPI_RXFIFORDY_FLAG
* - QSPI_TXFIFORDY_FLAG
* - QSPI_CMDSTS_FLAG
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
{
flag_status bit_status = RESET;
switch(flag)
{
case QSPI_RXFIFORDY_FLAG:
bit_status = (flag_status)qspi_x->fifosts_bit.rxfifordy;
break;
case QSPI_TXFIFORDY_FLAG:
bit_status = (flag_status)qspi_x->fifosts_bit.txfifordy;
break;
case QSPI_CMDSTS_FLAG:
bit_status = (flag_status)qspi_x->cmdsts_bit.cmdsts;
break;
default:
break;
}
return bit_status;
}
/**
* @brief clear flags
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param flag: flags to be clear
* this parameter can be one of the following values:
* - QSPI_CMDSTS_FLAG
* @retval none
*/
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
{
UNUSED(flag);
qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
}
/**
* @brief set dma threshold for dma rx
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_threshold: value to set
* this parameter can be one of the following values:
* - QSPI_DMA_FIFO_THOD_WORD08
* - QSPI_DMA_FIFO_THOD_WORD16
* - QSPI_DMA_FIFO_THOD_WORD32
* @retval none
*/
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
{
qspi_x->ctrl2_bit.rxfifo_thod = new_threshold;
}
/**
* @brief set dma threshold for dma tx
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_threshold: value to set
* this parameter can be one of the following values:
* - QSPI_DMA_FIFO_THOD_WORD08
* - QSPI_DMA_FIFO_THOD_WORD16
* - QSPI_DMA_FIFO_THOD_WORD32
* @retval none
*/
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
{
qspi_x->ctrl2_bit.txfifo_thod = new_threshold;
}
/**
* @brief enable/disable dma transfer
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state)
{
qspi_x->ctrl2_bit.dmaen = new_state;
}
/**
* @brief set wip position in status register of flash
* @note the function must be configured only when qspi in command-port mode!!!
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param busy_pos: value to set
* this parameter can be one of the following values:
* - QSPI_BUSY_OFFSET_0
* - QSPI_BUSY_OFFSET_1
* - QSPI_BUSY_OFFSET_2
* - QSPI_BUSY_OFFSET_3
* - QSPI_BUSY_OFFSET_4
* - QSPI_BUSY_OFFSET_5
* - QSPI_BUSY_OFFSET_6
* - QSPI_BUSY_OFFSET_7
* @retval none
*/
void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos)
{
qspi_x->ctrl_bit.busy = busy_pos;
}
/**
* @brief enable xip mode or command-port mode.
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
{
/* skip if state is no change */
if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel))
{
return;
}
/* wait until tx fifo emoty*/
while(qspi_x->fifosts_bit.txfifordy == 0);
/* flush and reset qspi state */
qspi_x->ctrl_bit.xiprcmdf = 1;
/* wait until action is finished */
while(qspi_x->ctrl_bit.abort);
/* set xip mode to new state */
qspi_x->ctrl_bit.xipsel = new_state;
/* wait until abort is not set */
while(qspi_x->ctrl_bit.abort);
/* wait until cache status valid*/
if(new_state == TRUE)
{
while( qspi_x->xip_cmd_w3_bit.csts );
}
}
/**
* @brief set command-port and qspi_x will start to work
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param qspi_cmd_struct: pointer to qspi cmd structure
* @retval none
*/
void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct)
{
uint32_t w1_val = 0, w3_val = 0;
/* config analyse cmd_w0 register */
qspi_x->cmd_w0 = (uint32_t)qspi_cmd_struct->address_code;
/* config analyse cmd_w1 register */
w1_val = (uint32_t)qspi_cmd_struct->address_length;
w1_val |= (uint32_t)(qspi_cmd_struct->second_dummy_cycle_num << 16);
w1_val |= (uint32_t)(qspi_cmd_struct->instruction_length << 24);
w1_val |= (uint32_t)(qspi_cmd_struct->pe_mode_enable << 28);
qspi_x->cmd_w1 = w1_val;
/* config analyse cmd_w2 register */
qspi_x->cmd_w2 = (uint32_t)qspi_cmd_struct->data_counter;
/* config analyse cmd_w3 register */
w3_val = (uint32_t)(qspi_cmd_struct->write_data_enable << 1);
w3_val |= (uint32_t)(qspi_cmd_struct->read_status_enable << 2);
w3_val |= (uint32_t)(qspi_cmd_struct->read_status_config << 3);
w3_val |= (uint32_t)(qspi_cmd_struct->operation_mode << 5);
w3_val |= (uint32_t)(qspi_cmd_struct->pe_mode_operate_code << 16);
w3_val |= (uint32_t)(qspi_cmd_struct->instruction_code << 24);
qspi_x->cmd_w3 = w3_val;
}
/**
* @brief initial xip mode for qspi_x
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1,QSPI2.
* @param xip_init_struct: pointer to xip init structure.
* @retval none.
*/
void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct)
{
uint32_t xc0_val = 0, xc1_val = 0, xc2_val = 0;
/* config analyse xip_cmd_w0 register */
xc0_val = (uint32_t)xip_init_struct->read_second_dummy_cycle_num;
xc0_val |= (uint32_t)(xip_init_struct->read_operation_mode << 8);
xc0_val |= (uint32_t)(xip_init_struct->read_address_length << 11);
xc0_val |= (uint32_t)(xip_init_struct->read_instruction_code << 12);
qspi_x->xip_cmd_w0 = xc0_val;
/* config analyse xip_cmd_w1 register */
xc1_val = (uint32_t)xip_init_struct->write_second_dummy_cycle_num;
xc1_val |= (uint32_t)(xip_init_struct->write_operation_mode << 8);
xc1_val |= (uint32_t)(xip_init_struct->write_address_length << 11);
xc1_val |= (uint32_t)(xip_init_struct->write_instruction_code << 12);
qspi_x->xip_cmd_w1 = xc1_val;
/* config analyse xip_cmd_w2 register */
xc2_val = (uint32_t)xip_init_struct->read_data_counter;
xc2_val |= (uint32_t)(xip_init_struct->read_time_counter << 8);
xc2_val |= (uint32_t)(xip_init_struct->read_select_mode << 15);
xc2_val |= (uint32_t)(xip_init_struct->write_data_counter << 16);
xc2_val |= (uint32_t)(xip_init_struct->write_time_counter << 24);
xc2_val |= (uint32_t)(xip_init_struct->write_select_mode << 31);
qspi_x->xip_cmd_w2 = xc2_val;
}
/**
* @brief read one byte from qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @retval 8-bit data.
*/
uint8_t qspi_byte_read(qspi_type* qspi_x)
{
return qspi_x->dt_u8;
}
/**
* @brief read one half-word from qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @retval 16-bit data.
*/
uint16_t qspi_half_word_read(qspi_type* qspi_x)
{
return qspi_x->dt_u16;
}
/**
* @brief read one word from qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @retval 32-bit data.
*/
uint32_t qspi_word_read(qspi_type* qspi_x)
{
return qspi_x->dt;
}
/**
* @brief write one byte to qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @param value: 8-bit data.
* @retval none.
*/
void qspi_byte_write(qspi_type* qspi_x, uint8_t value)
{
qspi_x->dt_u8 = value;
}
/**
* @brief write one half-word to qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @param value: 16-bit data.
* @retval none.
*/
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value)
{
qspi_x->dt_u16 = value;
}
/**
* @brief write one word to qspi device in command mode
* @param qspi_x: select the qspi peripheral.
* @param value: 32-bit data.
* @retval none.
*/
void qspi_word_write(qspi_type* qspi_x, uint32_t value)
{
qspi_x->dt = value;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c Normal file
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/**
**************************************************************************
* @file at32f435_437_scfg.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup SCFG
* @brief SCFG driver modules
* @{
*/
#ifdef SCFG_MODULE_ENABLED
/** @defgroup SCFG_private_functions
* @{
*/
/**
* @brief scfg reset
* @param none
* @retval none
*/
void scfg_reset(void)
{
crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
}
/**
* @brief scfg xmc address mapping swap set
* @param xmc_swap
* this parameter can be one of the following values:
* - SCFG_XMC_SWAP_NONE
* - SCFG_XMC_SWAP_MODE1
* - SCFG_XMC_SWAP_MODE2
* - SCFG_XMC_SWAP_MODE3
* @retval none
*/
void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
{
SCFG->cfg1_bit.swap_xmc = xmc_swap;
}
/**
* @brief scfg infrared config
* @param source
* this parameter can be one of the following values:
* - SCFG_IR_SOURCE_TMR10
* - SCFG_IR_SOURCE_USART1
* - SCFG_IR_SOURCE_USART2
* @param polarity
* this parameter can be one of the following values:
* - SCFG_IR_POLARITY_NO_AFFECTE
* - SCFG_IR_POLARITY_REVERSE
* @retval none
*/
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
{
SCFG->cfg1_bit.ir_src_sel = source;
SCFG->cfg1_bit.ir_pol = polarity;
}
/**
* @brief scfg memory address mapping set
* @param mem_map
* this parameter can be one of the following values:
* - SCFG_MEM_MAP_MAIN_MEMORY
* - SCFG_MEM_MAP_BOOT_MEMORY
* - SCFG_MEM_MAP_XMC_BANK1
* - SCFG_MEM_MAP_INTERNAL_SRAM
* - SCFG_MEM_MAP_XMC_SDRAM_BANK1
* @retval none
*/
void scfg_mem_map_set(scfg_mem_map_type mem_map)
{
SCFG->cfg1_bit.mem_map_sel = mem_map;
}
/**
* @brief scfg emac interface set
* @param mode
* this parameter can be one of the following values:
* - SCFG_EMAC_SELECT_MII
* - SCFG_EMAC_SELECT_RMII
* @retval none
*/
void scfg_emac_interface_set(scfg_emac_interface_type mode)
{
SCFG->cfg2_bit.mii_rmii_sel = mode;
}
/**
* @brief select the gpio pin used as exint line.
* @param port_source:
* select the gpio port to be used as source for exint lines.
* this parameter can be one of the following values:
* - SCFG_PORT_SOURCE_GPIOA
* - SCFG_PORT_SOURCE_GPIOB
* - SCFG_PORT_SOURCE_GPIOC
* - SCFG_PORT_SOURCE_GPIOD
* - SCFG_PORT_SOURCE_GPIOE
* - SCFG_PORT_SOURCE_GPIOF
* - SCFG_PORT_SOURCE_GPIOG
* - SCFG_PORT_SOURCE_GPIOH
* @param pin_source:
* specifies the exint line to be configured.
* this parameter can be one of the following values:
* - SCFG_PINS_SOURCE0
* - SCFG_PINS_SOURCE1
* - SCFG_PINS_SOURCE2
* - SCFG_PINS_SOURCE3
* - SCFG_PINS_SOURCE4
* - SCFG_PINS_SOURCE5
* - SCFG_PINS_SOURCE6
* - SCFG_PINS_SOURCE7
* - SCFG_PINS_SOURCE8
* - SCFG_PINS_SOURCE9
* - SCFG_PINS_SOURCE10
* - SCFG_PINS_SOURCE11
* - SCFG_PINS_SOURCE12
* - SCFG_PINS_SOURCE13
* - SCFG_PINS_SOURCE14
* - SCFG_PINS_SOURCE15
* @retval none
*/
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
switch (pin_source >> 0x02)
{
case 0:
SCFG->exintc1 &= ~tmp;
SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 1:
SCFG->exintc2 &= ~tmp;
SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 2:
SCFG->exintc3 &= ~tmp;
SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 3:
SCFG->exintc4 &= ~tmp;
SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
default:
break;
}
}
/**
* @brief enable or disable gpio pins ultra driven.
* @param value:
* this parameter can be one of the following values:
* - SCFG_ULTRA_DRIVEN_PB3
* - SCFG_ULTRA_DRIVEN_PB9
* - SCFG_ULTRA_DRIVEN_PB10
* - SCFG_ULTRA_DRIVEN_PD12
* - SCFG_ULTRA_DRIVEN_PD13
* - SCFG_ULTRA_DRIVEN_PD14
* - SCFG_ULTRA_DRIVEN_PD15
* - SCFG_ULTRA_DRIVEN_PF14
* - SCFG_ULTRA_DRIVEN_PF15
* @param new_state (TRUE or FALSE)
* @retval none
*/
void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
{
if(TRUE == new_state)
{
SCFG_REG(value) |= SCFG_REG_BIT(value);
}
else
{
SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_sdio.c Normal file
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/**
**************************************************************************
* @file at32f435_437_sdio.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup SDIO
* @brief SDIO driver modules
* @{
*/
#ifdef SDIO_MODULE_ENABLED
/** @defgroup SDIO_private_functions
* @{
*/
/**
* @brief reset the sdio register
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval none
*/
void sdio_reset(sdio_type *sdio_x)
{
sdio_x->pwrctrl = 0x0;
sdio_x->clkctrl = 0x0;
sdio_x->argu = 0x0;
sdio_x->cmdctrl = 0x0;
sdio_x->dttmr = 0x0;
sdio_x->dtlen = 0x0;
sdio_x->dtctrl = 0x0;
sdio_x->inten = 0x0;
sdio_x->intclr = 0x004007FF;
}
/**
* @brief set the power status of the controller
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param power_state
* this parameter can be one of the following values:
* - SDIO_POWER_OFF
* - SDIO_POWER_ON
* @retval none
*/
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
{
sdio_x->pwrctrl_bit.ps = power_state;
}
/**
* @brief get power status.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
*/
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
{
return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
}
/**
* @brief config sdio clock
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
* @param clk_edg
* this parameter can be one of the following values:
* - SDIO_CLOCK_EDGE_RISING
* - SDIO_CLOCK_EDGE_FALLING
* @retval none
*/
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
{
/* config clock edge */
sdio_x->clkctrl_bit.clkegs = clk_edg;
/* config clock divide [7:0] */
sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
/* config clock divide [9:8] */
sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
}
/**
* @brief config sdio bus width
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param width
* this parameter can be one of the following values:
* - SDIO_BUS_WIDTH_D1
* - SDIO_BUS_WIDTH_D4
* - SDIO_BUS_WIDTH_D8
* @retval none
*/
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
{
sdio_x->clkctrl_bit.busws = width;
}
/**
* @brief enable or disable clock divider bypss
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.bypsen = new_state;
}
/**
* @brief enable or disable power saving mode, config sdio_ck clock output
* when the bus is idle.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.pwrsven = new_state;
}
/**
* @brief enable or disable hardware flow control.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.hfcen = new_state;
}
/**
* @brief enable or disable sdio_ck output.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.clkoen = new_state;
}
/**
* @brief enable or disable dma.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.dmaen = new_state;
}
/**
* @brief config corresponding interrupt.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param int_opt
* this parameter can be one of the following values:
* - SDIO_CMDFAIL_INT
* - SDIO_DTFAIL_INT
* - SDIO_CMDTIMEOUT_INT
* - SDIO_DTTIMEOUT_INT
* - SDIO_TXERRU_INT
* - SDIO_RXERRO_INT
* - SDIO_CMDRSPCMPL_INT
* - SDIO_CMDCMPL_INT
* - SDIO_DTCMP_INT
* - SDIO_SBITERR_INT
* - SDIO_DTBLKCMPL_INT
* - SDIO_DOCMD_INT
* - SDIO_DOTX_INT
* - SDIO_DORX_INT
* - SDIO_TXBUFH_INT
* - SDIO_RXBUFH_INT
* - SDIO_TXBUFF_INT
* - SDIO_RXBUFF_INT
* - SDIO_TXBUFE_INT
* - SDIO_RXBUFE_INT
* - SDIO_TXBUF_INT
* - SDIO_RXBUF_INT
* - SDIO_SDIOIF_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state)
{
/* enable interrupt */
if(TRUE == new_state)
{
sdio_x->inten |= int_opt;
}
/* disable interrupt */
else
{
sdio_x->inten &= ~(int_opt);
}
}
/**
* @brief get sdio flag.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param flag
* this parameter can be one of the following values:
* - SDIO_CMDFAIL_FLAG
* - SDIO_DTFAIL_FLAG
* - SDIO_CMDTIMEOUT_FLAG
* - SDIO_DTTIMEOUT_FLAG
* - SDIO_TXERRU_FLAG
* - SDIO_RXERRO_FLAG
* - SDIO_CMDRSPCMPL_FLAG
* - SDIO_CMDCMPL_FLAG
* - SDIO_DTCMPL_FLAG
* - SDIO_SBITERR_FLAG
* - SDIO_DTBLKCMPL_FLAG
* - SDIO_DOCMD_FLAG
* - SDIO_DOTX_FLAG
* - SDIO_DORX_FLAG
* - SDIO_TXBUFH_FLAG
* - SDIO_RXBUFH_FLAG
* - SDIO_TXBUFF_FLAG
* - SDIO_RXBUFF_FLAG
* - SDIO_TXBUFE_FLAG
* - SDIO_RXBUFE_FLAG
* - SDIO_TXBUF_FLAG
* - SDIO_RXBUF_FLAG
* - SDIO_SDIOIF_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
{
flag_status status = RESET;
if((sdio_x->sts & flag) == flag)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief clear sdio flag.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param int_opt
* this parameter can be any combination of the following values:
* - SDIO_CMDFAIL_FLAG
* - SDIO_DTFAIL_FLAG
* - SDIO_CMDTIMEOUT_FLAG
* - SDIO_DTTIMEOUT_FLAG
* - SDIO_TXERRU_FLAG
* - SDIO_RXERRO_FLAG
* - SDIO_CMDRSPCMPL_FLAG
* - SDIO_CMDCMPL_FLAG
* - SDIO_DTCMPL_FLAG
* - SDIO_SBITERR_FLAG
* - SDIO_DTBLKCMPL_FLAG
* - SDIO_SDIOIF_FLAG
* @retval none
*/
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
{
sdio_x->intclr = flag;
}
/**
* @brief config sdio command.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param command_struct : pointer to a sdio_command_struct_type structure
* that contains the configuration information for the sdio command.
* @retval none
*/
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
{
/* disable command path state machine */
sdio_x->cmdctrl_bit.ccsmen = FALSE;
/* config command argument */
sdio_x->argu = command_struct->argument;
/* config command register */
sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
}
/**
* @brief enable or disable command path state machine(CPSM).
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->cmdctrl_bit.ccsmen = new_state;
}
/**
* @brief get command index of last command for which response received.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval uint8_t: command index
*/
uint8_t sdio_command_response_get(sdio_type *sdio_x)
{
return sdio_x->rspcmd_bit.rspcmd;
}
/**
* @brief get response received from the card for the last command.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param reg_index
* this parameter can be one of the following values:
* - SDIO_RSP1_INDEX
* - SDIO_RSP2_INDEX
* - SDIO_RSP3_INDEX
* - SDIO_RSP4_INDEX
* @retval uint32_t: response register value
*/
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
{
uint32_t response_value = 0;
switch(reg_index)
{
case SDIO_RSP1_INDEX:
response_value = sdio_x->rsp1;
break;
case SDIO_RSP2_INDEX:
response_value = sdio_x->rsp2;
break;
case SDIO_RSP3_INDEX:
response_value = sdio_x->rsp3;
break;
case SDIO_RSP4_INDEX:
response_value = sdio_x->rsp4;
break;
default: break;
}
return response_value;
}
/**
* @brief config sdio data.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param data_struct : pointer to a sdio_data_struct_type structure
* that contains the configuration information for the sdio data.
* @retval none
*/
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
{
/* disable data path state machine */
sdio_x->dtctrl_bit.tfren = FALSE;
/* config data block, transfer mode and transfer direction */
sdio_x->dtctrl_bit.blksize = data_struct->block_size;
sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
/* config data length */
sdio_x->dtlen_bit.dtlen = data_struct->data_length;
/* config data transfer timeout */
sdio_x->dttmr_bit.timeout = data_struct->timeout;
}
/**
* @brief enable or disable data path state machine(DPSM).
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.tfren = new_state;
}
/**
* @brief get the number of remaining data bytes to be transferred.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: number of bytes
*/
uint32_t sdio_data_counter_get(sdio_type *sdio_x)
{
return sdio_x->dtcnt;
}
/**
* @brief read a word data from sdio fifo.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: data received
*/
uint32_t sdio_data_read(sdio_type *sdio_x)
{
return sdio_x->buf;
}
/**
* @brief get the number of words left to be written to or read from fifo..
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: number of words
*/
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
{
return sdio_x->bufcnt;
}
/**
* @brief write one word data to fifo.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param data: data to be transferred.
* @retval none
*/
void sdio_data_write(sdio_type *sdio_x, uint32_t data)
{
sdio_x->buf = data;
}
/**
* @brief set the read wait mode.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param mode
* this parameter can be one of the following values:
* - SDIO_READ_WAIT_CONTROLLED_BY_D2
* - SDIO_READ_WAIT_CONTROLLED_BY_CK
* @retval none
*/
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
{
sdio_x->dtctrl_bit.rdwtmode = mode;
}
/**
* @brief enable or disable to start sd i/o read wait operation.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.rdwtstart = new_state;
}
/**
* @brief enable or disable to stop sd i/o read wait operation.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.rdwtstop = new_state;
}
/**
* @brief enable or disable the sd i/o function.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.ioen = new_state;
}
/**
* @brief enable or disable sd i/o suspend command sending.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->cmdctrl_bit.iosusp = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_spi.c Normal file
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/**
**************************************************************************
* @file at32f435_437_spi.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
#ifdef SPI_MODULE_ENABLED
/** @defgroup SPI_private_functions
* @{
*/
/**
* @brief spi reset by crm reset register
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval none
*/
void spi_i2s_reset(spi_type *spi_x)
{
if(spi_x == SPI1)
{
crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI2)
{
crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI3)
{
crm_periph_reset(CRM_SPI3_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI3_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI4)
{
crm_periph_reset(CRM_SPI4_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI4_PERIPH_RESET, FALSE);
}
}
/**
* @brief spi init config with its default value.
* @param spi_init_struct : pointer to a spi_init_type structure which will
* be initialized.
* @retval none
*/
void spi_default_para_init(spi_init_type* spi_init_struct)
{
spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
}
/**
* @brief spi init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
* @retval none
*/
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
{
spi_x->i2sctrl_bit.i2smsel = FALSE;
if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = TRUE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = TRUE;
spi_x->ctrl1_bit.ora = FALSE;
}
spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
{
spi_x->ctrl1_bit.swcsil = TRUE;
}
else
{
spi_x->ctrl1_bit.swcsil = FALSE;
}
spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
if(spi_init_struct->mclk_freq_division <= SPI_MCLK_DIV_256)
{
spi_x->ctrl2_bit.mdiv3en = FALSE;
spi_x->ctrl2_bit.mdiv_h = FALSE;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
}
else if(spi_init_struct->mclk_freq_division == SPI_MCLK_DIV_3)
{
spi_x->ctrl2_bit.mdiv3en = TRUE;
spi_x->ctrl2_bit.mdiv_h = FALSE;
spi_x->ctrl1_bit.mdiv_l = 0;
}
else
{
spi_x->ctrl2_bit.mdiv3en = FALSE;
spi_x->ctrl2_bit.mdiv_h = TRUE;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
}
spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
}
/**
* @brief enable or disable the ti mode for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of ti mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.tien = new_state;
}
/**
* @brief spi next transmit crc for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval none
*/
void spi_crc_next_transmit(spi_type* spi_x)
{
spi_x->ctrl1_bit.ntc = TRUE;
}
/**
* @brief set the crc polynomial value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param crc_poly: crc polynomial value.
* @retval none
*/
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
{
spi_x->cpoly_bit.cpoly = crc_poly;
}
/**
* @brief return the crc polynomial register value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval the select crc polynomial register value
*/
uint16_t spi_crc_polynomial_get(spi_type* spi_x)
{
return spi_x->cpoly_bit.cpoly;
}
/**
* @brief enable or disable the hardware crc calculation for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of crc calculation.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.ccen = new_state;
}
/**
* @brief return the transmit or the receive crc value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param crc_direction: select transmit or receive crc value to be read
* - SPI_CRC_RX
* - SPI_CRC_TX
* @retval the select crc register value
*/
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
{
if(crc_direction == SPI_CRC_RX)
return spi_x->rcrc_bit.rcrc;
else
return spi_x->tcrc_bit.tcrc;
}
/**
* @brief enable or disable the hardware cs output for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of spi master cs output.
* this parameter can be: TRUE or FALSE.
* note:the bit only use in spi master mode
* @retval none
*/
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.hwcsoe = new_state;
}
/**
* @brief set the software cs internal level for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param level: set the state of spi cs level.
* this parameter can be one of the following values:
* - SPI_SWCS_INTERNAL_LEVEL_LOW
* - SPI_SWCS_INTERNAL_LEVEL_HIGHT
* note:the bit only use when swcsen bit is set.
* note:when use this bit,io operation on the cs pin are invalid.
* @retval none
*/
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
{
spi_x->ctrl1_bit.swcsil = level;
}
/**
* @brief set the data frame bit num for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param bit_num: set the data frame size
* - SPI_FRAME_8BIT
* - SPI_FRAME_16BIT
* @retval none
*/
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
{
spi_x->ctrl1_bit.fbn = bit_num;
}
/**
* @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param direction: data transfer direction
* this parameter can be one of the following values:
* - SPI_HALF_DUPLEX_DIRECTION_RX
* - SPI_HALF_DUPLEX_DIRECTION_TX
* @retval none
*/
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
{
spi_x->ctrl1_bit.slbtd = direction;
}
/**
* @brief enable or disable spi.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of spi.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.spien = new_state;
}
/**
* @brief i2s init config with its default value.
* @param i2s_init_struct : pointer to a i2s_init_type structure which will
* be initialized.
* @retval none
*/
void i2s_default_para_init(i2s_init_type* i2s_init_struct)
{
i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
i2s_init_struct->mclk_output_enable = FALSE;
}
/**
* @brief i2s init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
* @retval none
*/
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
{
crm_clocks_freq_type clocks_freq;
uint32_t i2s_sclk_index = 0;
uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
/* i2s audio frequency config */
if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
else
{
crm_clocks_freq_get(&clocks_freq);
i2s_sclk_index = clocks_freq.sclk_freq;
if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
else
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
}
frequency_index = frequency_index / 10;
i2sodd_index = frequency_index & (uint16_t)0x0001;
i2sdiv_index = (frequency_index - i2sodd_index) / 2;
if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
spi_x->i2sclk_bit.i2sodd = i2sodd_index;
if(i2sdiv_index > 0x00FF)
{
spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
}
else
{
spi_x->i2sclk_bit.i2sdiv_h = 0;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
}
/* i2s audio_protocol set*/
if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
{
spi_x->i2sctrl_bit.pcmfssel = 1;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 2;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 1;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 0;
}
/* i2s data_channel_format set*/
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
{
spi_x->i2sctrl_bit.i2scbn = 0;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 1;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 2;
}
spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
spi_x->i2sctrl_bit.i2smsel = TRUE;
}
/**
* @brief enable or disable i2s.
* @param spi_x: select the i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param new_state: new state of i2s.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void i2s_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->i2sctrl_bit.i2sen = new_state;
}
/**
* @brief enable or disable the specified spi/i2s interrupts.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - SPI_I2S_ERROR_INT
* - SPI_I2S_RDBF_INT
* - SPI_I2S_TDBE_INT
* @param new_state: new state of the specified spi/i2s interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
{
if(new_state != FALSE)
{
spi_x->ctrl2 |= spi_i2s_int;
}
else
{
spi_x->ctrl2 &= ~spi_i2s_int;
}
}
/**
* @brief enable or disable the spi/i2s dma transmitter mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaten = new_state;
}
/**
* @brief enable or disable the spi/i2s dma receiver mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaren = new_state;
}
/**
* @brief spi/i2s data transmit
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param tx_data: the data to be transmit.
* this parameter can be:
* - (0x0000~0xFFFF)
* @retval none
*/
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
{
spi_x->dt = tx_data;
}
/**
* @brief spi/i2s data receive
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @retval the received data value
*/
uint16_t spi_i2s_data_receive(spi_type* spi_x)
{
return (uint16_t)spi_x->dt;
}
/**
* @brief get flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_ACS_FLAG (this flag only use in i2s mode)
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* - SPI_I2S_BF_FLAG
* - SPI_CSPAS_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
if ((spi_x->sts & spi_i2s_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_CCERR_FLAG
* - SPI_I2S_RDBF_FLAG
* - I2S_TUERR_FLAG
* - SPI_MMERR_FLAG
* - SPI_I2S_ROERR_FLAG
* - SPI_CSPAS_FLAG
* @note
* SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
* I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
* SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
* @retval none
*/
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
UNUSED(spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_CSPAS_FLAG)
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_MMERR_FLAG)
{
UNUSED(spi_x->sts);
spi_x->ctrl1 = spi_x->ctrl1;
}
else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
{
UNUSED(spi_x->dt);
UNUSED(spi_x->sts);
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_usart.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup USART
* @brief USART driver modules
* @{
*/
#ifdef USART_MODULE_ENABLED
/** @defgroup USART_private_functions
* @{
*/
/**
* @brief deinitialize the usart peripheral registers to their default reset values.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
* @retval none
*/
void usart_reset(usart_type* usart_x)
{
if(usart_x == USART1)
{
crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
}
else if(usart_x == USART2)
{
crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
}
else if(usart_x == USART3)
{
crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE);
}
else if(usart_x == UART4)
{
crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_UART4_PERIPH_RESET, FALSE);
}
else if(usart_x == UART5)
{
crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE);
}
else if(usart_x == USART6)
{
crm_periph_reset(CRM_USART6_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART6_PERIPH_RESET, FALSE);
}
else if(usart_x == UART7)
{
crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE);
}
else if(usart_x == UART8)
{
crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the usart peripheral according to the specified parameters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
* @param baud_rate: configure the usart communication baud rate.
* @param data_bit: data bits transmitted or received in a frame
* this parameter can be one of the following values:
* - USART_DATA_7BITS
* - USART_DATA_8BITS
* - USART_DATA_9BITS.
* @param stop_bit: stop bits transmitted
* this parameter can be one of the following values:
* - USART_STOP_1_BIT
* - USART_STOP_0_5_BIT.
* - USART_STOP_2_BIT
* - USART_STOP_1_5_BIT.
* @retval none
*/
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
{
crm_clocks_freq_type clocks_freq;
uint32_t apb_clock, temp_val;
crm_clocks_freq_get(&clocks_freq);
if((usart_x == USART1) || (usart_x == USART6))
{
apb_clock = clocks_freq.apb2_freq;
}
else
{
apb_clock = clocks_freq.apb1_freq;
}
temp_val = (apb_clock * 10 / baud_rate);
if((temp_val % 10) < 5)
{
temp_val = (temp_val / 10);
}
else
{
temp_val = (temp_val / 10) + 1;
}
usart_x->baudr_bit.div = temp_val;
if(data_bit == USART_DATA_7BITS)
{
usart_x->ctrl1_bit.dbn_h = 1;
usart_x->ctrl1_bit.dbn_l = 0;
}
else if(data_bit == USART_DATA_8BITS)
{
usart_x->ctrl1_bit.dbn_h = 0;
usart_x->ctrl1_bit.dbn_l = 0;
}
else
{
usart_x->ctrl1_bit.dbn_h = 0;
usart_x->ctrl1_bit.dbn_l = 1;
}
usart_x->ctrl2_bit.stopbn = stop_bit;
}
/**
* @brief usart parity selection config.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
* @param parity: select the none, odd or even parity.
* this parameter can be one of the following values:
* - USART_PARITY_NONE
* - USART_PARITY_EVEN.
* - USART_PARITY_ODD
* @retval none
*/
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
{
if(parity == USART_PARITY_NONE)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = FALSE;
}
else if(parity == USART_PARITY_EVEN)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = TRUE;
}
else if(parity == USART_PARITY_ODD)
{
usart_x->ctrl1_bit.psel = TRUE;
usart_x->ctrl1_bit.pen = TRUE;
}
}
/**
* @brief enable or disable the specified usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.uen = new_state;
}
/**
* @brief usart transmitter enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ten = new_state;
}
/**
* @brief usart receiver enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ren = new_state;
}
/**
* @brief usart clock config.
* @note clock config are not available for UART4, UART5, UART7 and UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param clk_pol: polarity of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_POLARITY_LOW
* - USART_CLOCK_POLARITY_HIGH
* @param clk_pha: phase of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_PHASE_1EDGE
* - USART_CLOCK_PHASE_2EDGE
* @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_LAST_BIT_NONE
* - USART_CLOCK_LAST_BIT_OUTPUT
* @retval none
*/
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
{
usart_x->ctrl2_bit.clkpol = clk_pol;
usart_x->ctrl2_bit.clkpha = clk_pha;
usart_x->ctrl2_bit.lbcp = clk_lb;
}
/**
* @brief usart enable the ck pin.
* @note clock enable are not available for UART4, UART5, UART7 and UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param new_state: TRUE or FALSE
* @retval none
*/
void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.clken = new_state;
}
/**
* @brief enable or disable the specified usart interrupts.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - USART_IDLE_INT: idle interrupt
* - USART_RDBF_INT: rdbf interrupt
* - USART_TDC_INT: tdc interrupt
* - USART_TDBE_INT: tdbe interrupt
* - USART_PERR_INT: perr interrupt
* - USART_BF_INT: break frame interrupt
* - USART_ERR_INT: err interrupt
* - USART_CTSCF_INT: ctscf interrupt
* @param new_state: new state of the specified usart interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
{
if(new_state == TRUE)
PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
else
PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
}
/**
* @brief enable or disable the usart's dma transmitter interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaten = new_state;
}
/**
* @brief enable or disable the usart's dma receiver interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaren = new_state;
}
/**
* @brief set the wakeup id of the usart.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param usart_id: the matching id(0x0~0xFF).
* @retval none
*/
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
{
if(usart_x->ctrl2_bit.idbn == USART_ID_FIXED_4_BIT)
{
usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
usart_x->ctrl2_bit.id_h = 0;
}
else
{
usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
usart_x->ctrl2_bit.id_h = ((usart_id & 0xF0) >> 4);
}
}
/**
* @brief select the usart wakeup method in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param wakeup_mode: determines the way to wake up usart method.
* this parameter can be one of the following values:
* - USART_WAKEUP_BY_IDLE_FRAME
* - USART_WAKEUP_BY_MATCHING_ID
* @retval none
*/
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
{
usart_x->ctrl1_bit.wum = wakeup_mode;
}
/**
* @brief config the usart in mute mode in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the usart mute mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.rm = new_state;
}
/**
* @brief set the usart break frame bit num.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param break_bit: specifies the break bit num.
* this parameter can be one of the following values:
* - USART_BREAK_10BITS
* - USART_BREAK_11BITS
* @retval none
*/
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
{
usart_x->ctrl2_bit.bfbn = break_bit;
}
/**
* @brief enable or disable the usart lin mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the usart lin mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.linen = new_state;
}
/**
* @brief transmit single data through the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param data: the data to transmit.
* @retval none
*/
void usart_data_transmit(usart_type* usart_x, uint16_t data)
{
usart_x->dt = (data & 0x01FF);
}
/**
* @brief return the most recent received data by the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @retval the received data.
*/
uint16_t usart_data_receive(usart_type* usart_x)
{
return (uint16_t)(usart_x->dt);
}
/**
* @brief transmit break characters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @retval none
*/
void usart_break_send(usart_type* usart_x)
{
usart_x->ctrl1_bit.sbf = TRUE;
}
/**
* @brief config the specified usart smartcard guard time.
* @note The guard time bits are not available for UART4, UART5, UART7 or UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param guard_time_val: specifies the guard time (0x00~0xFF).
* @retval none
*/
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
{
usart_x->gdiv_bit.scgt = guard_time_val;
}
/**
* @brief config the irda/smartcard division.
* @note the division are not available for UART4, UART5, UART7 or UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param div_val: specifies the division.
* @retval none
*/
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
{
usart_x->gdiv_bit.isdiv = div_val;
}
/**
* @brief enable or disable the usart smart card mode.
* @note the smart card mode are not available for UART4, UART5, UART7 or UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param new_state: new state of the smart card mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scmen = new_state;
}
/**
* @brief enable or disable nack transmission in smartcard mode.
* @note the smart card nack are not available for UART4, UART5, UART7 or UART8.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3 or USART6.
* @param new_state: new state of the nack transmission.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scnacken = new_state;
}
/**
* @brief enable or disable the usart single line bidirectional half-duplex communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the single line half-duplex select.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.slben = new_state;
}
/**
* @brief enable or disable the usart's irda interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdaen = new_state;
}
/**
* @brief configure the usart's irda low power.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdalp = new_state;
}
/**
* @brief configure the usart's hardware flow control.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3
* @param flow_state: specifies the hardware flow control.
* this parameter can be one of the following values:
* - USART_HARDWARE_FLOW_NONE
* - USART_HARDWARE_FLOW_RTS,
* - USART_HARDWARE_FLOW_CTS,
* - USART_HARDWARE_FLOW_RTS_CTS
* @retval none
*/
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
{
if(flow_state == USART_HARDWARE_FLOW_NONE)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_CTS)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
}
/**
* @brief check whether the specified usart flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
{
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear the usart's pending flags.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
* @param flag: specifies the flag to clear.
* this parameter can be any combination of the following values:
* - USART_CTSCF_FLAG: (not available for UART4,UART5,USART6,UART7 and UART8).
* - USART_BFF_FLAG:
* - USART_TDC_FLAG:
* - USART_RDBF_FLAG:
* - USART_PERR_FLAG:
* - USART_FERR_FLAG:
* - USART_NERR_FLAG:
* - USART_ROERR_FLAG:
* - USART_IDLEF_FLAG:
* @note
* - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
* sequence: a read operation to usart sts register (usart_flag_get())
* followed by a read operation to usart dt register (usart_data_receive()).
* - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
* - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
* followed by a write operation to usart dt register (usart_data_transmit()).
* - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
* @retval none
*/
void usart_flag_clear(usart_type* usart_x, uint32_t flag)
{
if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
{
UNUSED(usart_x->sts);
UNUSED(usart_x->dt);
}
else
{
usart_x->sts = ~flag;
}
}
/**
* @brief configure the usart's rs485 transmit delay time.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3
* @param start_delay_time: transmit start delay time.
* @param complete_delay_time: transmit complete delay time.
* @retval none
*/
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time)
{
usart_x->ctrl1_bit.tsdt = start_delay_time;
usart_x->ctrl1_bit.tcdt = complete_delay_time;
}
/**
* @brief swap the usart's transmit receive pin.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.trpswap = new_state;
}
/**
* @brief set the usart's identification bit num.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
* @param id_bit_num: the usart wakeup identification bit num.
* this parameter can be: USART_ID_FIXED_4_BIT or USART_ID_RELATED_DATA_BIT.
* @retval none
*/
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num)
{
usart_x->ctrl2_bit.idbn = (uint8_t)id_bit_num;
}
/**
* @brief set the usart's de polarity.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3
* @param de_polarity: the usart de polarity selection.
* this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
* @retval none
*/
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
{
usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
}
/**
* @brief enable or disable the usart's rs485 mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.rs485en = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_wdt.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup WDT
* @brief WDT driver modules
* @{
*/
#ifdef WDT_MODULE_ENABLED
/** @defgroup WDT_private_functions
* @{
*/
/**
* @brief wdt enable ,the reload value will be sent to the counter
* @param none
* @retval none
*/
void wdt_enable(void)
{
WDT->cmd = WDT_CMD_ENABLE;
}
/**
* @brief reload wdt counter
* @param none
* @retval none
*/
void wdt_counter_reload(void)
{
WDT->cmd = WDT_CMD_RELOAD;
}
/**
* @brief set wdt counter reload value
* @param reload_value (0x0000~0x0FFF)
* @retval none
*/
void wdt_reload_value_set(uint16_t reload_value)
{
WDT->rld = reload_value;
}
/**
* @brief set wdt division divider
* @param division
* this parameter can be one of the following values:
* - WDT_CLK_DIV_4
* - WDT_CLK_DIV_8
* - WDT_CLK_DIV_16
* - WDT_CLK_DIV_32
* - WDT_CLK_DIV_64
* - WDT_CLK_DIV_128
* - WDT_CLK_DIV_256
* @retval none
*/
void wdt_divider_set(wdt_division_type division)
{
WDT->div_bit.div = division;
}
/**
* @brief enable or disable wdt cmd register write
* @param new_state (TRUE or FALSE)
* @retval none
*/
void wdt_register_write_enable( confirm_state new_state)
{
if(new_state == FALSE)
{
WDT->cmd = WDT_CMD_LOCK;
}
else
{
WDT->cmd = WDT_CMD_UNLOCK;
}
}
/**
* @brief get wdt flag
* @param wdt_flag
* this parameter can be one of the following values:
* - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
* - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
* - WDT_WINF_UPDATE_FLAG: window value update complete flag.
* @retval state of wdt flag
*/
flag_status wdt_flag_get(uint16_t wdt_flag)
{
flag_status status = RESET;
if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief wdt window counter value set
* @param window_cnt (0x0000~0x0FFF)
* @retval none
*/
void wdt_window_counter_set(uint16_t window_cnt)
{
WDT->win_bit.win = window_cnt;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_wwdt.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup WWDT
* @brief WWDT driver modules
* @{
*/
#ifdef WWDT_MODULE_ENABLED
/** @defgroup WWDT_private_functions
* @{
*/
/**
* @brief wwdt reset by crm reset register
* @retval none
*/
void wwdt_reset(void)
{
crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
}
/**
* @brief wwdt division set
* @param division
* this parameter can be one of the following values:
* - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
* - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
* - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
* - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
* @retval none
*/
void wwdt_divider_set(wwdt_division_type division)
{
WWDT->cfg_bit.div = division;
}
/**
* @brief wwdt reload counter interrupt flag clear
* @param none
* @retval none
*/
void wwdt_flag_clear(void)
{
WWDT->sts = 0;
}
/**
* @brief wwdt enable and the counter value load
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_enable(uint8_t wwdt_cnt)
{
WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
}
/**
* @brief wwdt reload counter interrupt enable
* @param none
* @retval none
*/
void wwdt_interrupt_enable(void)
{
WWDT->cfg_bit.rldien = TRUE;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_flag_get(void)
{
return (flag_status)WWDT->sts_bit.rldf;
}
/**
* @brief wwdt counter value set
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_counter_set(uint8_t wwdt_cnt)
{
WWDT->ctrl_bit.cnt = wwdt_cnt;
}
/**
* @brief wwdt window counter value set
* @param window_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_window_counter_set(uint8_t window_cnt)
{
WWDT->cfg_bit.win = window_cnt;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_xmc.c
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_conf.h"
/** @addtogroup AT32F435_437_periph_driver
* @{
*/
/** @defgroup XMC
* @brief XMC driver modules
* @{
*/
#ifdef XMC_MODULE_ENABLED
/** @defgroup XMC_private_functions
* @{
*/
/**
* @brief xmc nor or sram registers reset
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM4
* @retval none
*/
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
{
/* XMC_BANK1_NORSRAM1 */
if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
}
/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
else
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
}
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
}
/**
* @brief initialize the xmc nor/sram banks according to the specified
* parameters in the xmc_norsraminitstruct.
* @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @retval none
*/
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
{
/* bank1 nor/sram control register configuration */
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
xmc_norsram_init_struct->device |
xmc_norsram_init_struct->bus_type |
xmc_norsram_init_struct->burst_mode_enable |
xmc_norsram_init_struct->asynwait_enable |
xmc_norsram_init_struct->wait_signal_lv |
xmc_norsram_init_struct->wrapped_mode_enable |
xmc_norsram_init_struct->wait_signal_config |
xmc_norsram_init_struct->write_enable |
xmc_norsram_init_struct->wait_signal_enable |
xmc_norsram_init_struct->write_timing_enable |
xmc_norsram_init_struct->write_burst_syn;
/* if nor flash device */
if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
{
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
}
}
/**
* @brief initialize the xmc nor/sram banks according to the specified
* parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
* @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @retval none
*/
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
/* bank1 nor/sram timing register configuration */
XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
(uint32_t)xmc_rw_timing_struct->addr_setup_time |
(xmc_rw_timing_struct->addr_hold_time << 4) |
(xmc_rw_timing_struct->data_setup_time << 8) |
(xmc_rw_timing_struct->bus_latency_time <<16) |
(xmc_rw_timing_struct->clk_psc << 20) |
(xmc_rw_timing_struct->data_latency_time << 24) |
xmc_rw_timing_struct->mode;
/* bank1 nor/sram timing register for write configuration, if extended mode is used */
if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
{
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
(uint32_t)xmc_w_timing_struct->addr_setup_time |
(xmc_w_timing_struct->addr_hold_time << 4) |
(xmc_w_timing_struct->data_setup_time << 8) |
(xmc_w_timing_struct->bus_latency_time << 16) |
(xmc_w_timing_struct->clk_psc << 20) |
(xmc_w_timing_struct->data_latency_time << 24) |
xmc_w_timing_struct->mode;
}
else
{
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
}
}
/**
* @brief fill each xmc_nor_sram_init_struct member with its default value.
* @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
{
/* reset nor/sram init structure parameters values */
xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
}
/**
* @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
* @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
* structure which will be initialized.
* @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_rw_timing_struct->addr_setup_time = 0xF;
xmc_rw_timing_struct->addr_hold_time = 0xF;
xmc_rw_timing_struct->data_setup_time = 0xFF;
xmc_rw_timing_struct->bus_latency_time = 0xF;
xmc_rw_timing_struct->clk_psc = 0xF;
xmc_rw_timing_struct->data_latency_time = 0xF;
xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_w_timing_struct->addr_setup_time = 0xF;
xmc_w_timing_struct->addr_hold_time = 0xF;
xmc_w_timing_struct->data_setup_time = 0xFF;
xmc_w_timing_struct->bus_latency_time = 0xF;
xmc_w_timing_struct->clk_psc = 0xF;
xmc_w_timing_struct->data_latency_time = 0xF;
xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
}
/**
* @brief enable or disable the specified nor/sram memory bank.
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM4
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
}
/**
* @brief config the bus turnaround phase.
* @param xmc_sub_bank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM4
* @param w2w_timing :write timing
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
}
/**
* @brief xmc nand flash registers reset
* @param xmc_bank
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @retval none
*/
void xmc_nand_reset(xmc_class_bank_type xmc_bank)
{
/* set the xmc_bank2_nand registers to their reset values */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = 0x00000018;
XMC_BANK2->bk2is = 0x00000040;
XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
}
/* set the xmc_bank3_nand registers to their reset values */
else
{
XMC_BANK3->bk3ctrl = 0x00000018;
XMC_BANK3->bk3is = 0x00000040;
XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_nand_init_struct : pointer to a xmc_nand_init_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
{
uint32_t tempctrl = 0x0;
/* Set the tempctrl value according to xmc_nand_init_struct parameters */
tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
xmc_nand_init_struct->bus_type |
xmc_nand_init_struct->ecc_enable |
xmc_nand_init_struct->ecc_pagesize |
(xmc_nand_init_struct->delay_time_cycle << 9) |
(xmc_nand_init_struct->delay_time_ar << 13) |
0x00000008;
/* xmc_bank2_nand registers configuration */
if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = tempctrl;
}
/* xmc_bank3_nand registers configuration */
else
{
XMC_BANK3->bk3ctrl = tempctrl;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
{
uint32_t tempmem = 0x0, tempatt = 0x0;
/* set the tempmem value according to xmc_nand_init_struct parameters */
tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
/* set the tempatt value according to xmc_nand_init_struct parameters */
tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
(xmc_special_spacetiming_struct->mem_waite_time << 8) |
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* xmc_bank2_nand registers configuration */
if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2tmgatt = tempatt;
XMC_BANK2->bk2tmgmem = tempmem;
}
else
{
XMC_BANK3->bk3tmgatt = tempatt;
XMC_BANK3->bk3tmgmem = tempmem;
}
}
/**
* @brief fill each xmc_nand_init_struct member with its default value.
* @param xmc_nand_init_struct: pointer to a xmc_nand_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
{
/* reset nand init structure parameters values */
xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
xmc_nand_init_struct->delay_time_cycle = 0x0;
xmc_nand_init_struct->delay_time_ar = 0x0;
}
/**
* @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* structure which will be initialized.
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
{
xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
}
/**
* @brief enable or disable the specified nand memory bank.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.en = new_state;
}
/* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.en = new_state;
}
}
/**
* @brief enable or disable the xmc nand ecc feature.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.eccen = new_state;
}
/* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
else
{
XMC_BANK3->bk3ctrl_bit.eccen = new_state;
}
}
/**
* @brief return the error correction code register value.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* @retval the error correction code (ecc) value.
*/
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
{
uint32_t eccvaule = 0x0;
/* get the bk2ecc register value */
if(xmc_bank == XMC_BANK2_NAND)
{
eccvaule = XMC_BANK2->bk2ecc;
}
/* get the bk3ecc register value */
else
{
eccvaule = XMC_BANK3->bk3ecc;
}
/* return the error correction code value */
return eccvaule;
}
/**
* @brief xmc sdram registers reset
* @param xmc_bank
* this parameter can be one of the following values:
* - XMC_SDRAM_BANK1
* - XMC_SDRAM_BANK2
* @retval none
*/
void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
{
XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
XMC_SDRAM->tm[xmc_bank] = 0x0FFFFFFF;
XMC_SDRAM->cmd = 0x00000000;
XMC_SDRAM->rcnt = 0x00000000;
XMC_SDRAM->sts = 0x00000000;
}
/**
* @brief initialize the xmc sdram banks according to the specified
* parameters in the xmc_sdram_init_struct and xmc_sdram_timing_struct.
* @param xmc_sdram_init_struct : pointer to a xmc_sdram_init_type
* structure that contains the configuration information for the xmc
* sdram specified banks.
* @param xmc_sdram_timing_struct : pointer to a xmc_sdram_timing_type
* structure that contains the configuration information for the xmc
* sdram specified banks.
* @retval none
*/
void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
{
if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
{
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
}
if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
{
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
/* sdctrl2 bstr is not care */
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
/* sdctrl2 clkdiv is not care */
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
/* sdtm2 trc is not care */
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
/* sdtm2 trp is not care */
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
}
}
/**
* @brief fill each xmc_sdram_init_struct member with its default value.
* @param xmc_sdram_init_struct: pointer to a xmc_sdram_init_type
* structure which will be initialized.
* @param xmc_sdram_timing_struct: pointer to a xmc_sdram_timing_type
* structure which will be initialized.
* @retval none
*/
void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
{
/* reset sdram init structure parameters values */
xmc_sdram_init_struct->sdram_bank = XMC_SDRAM_BANK1;
xmc_sdram_init_struct->internel_banks = XMC_INBK_4;
xmc_sdram_init_struct->clkdiv = XMC_NO_CLK;
xmc_sdram_init_struct->write_protection = FALSE;
xmc_sdram_init_struct->burst_read = FALSE;
xmc_sdram_init_struct->column_address = XMC_COLUMN_8;
xmc_sdram_init_struct->row_address = XMC_ROW_11;
xmc_sdram_init_struct->cas = XMC_CAS_1;
xmc_sdram_init_struct->width = XMC_MEM_WIDTH_8;
xmc_sdram_init_struct->read_delay = XMC_READ_DELAY_1;
xmc_sdram_timing_struct->tmrd = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->txsr = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->tras = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->trc = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->twr = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->trp = XMC_DELAY_CYCLE_16;
xmc_sdram_timing_struct->trcd = XMC_DELAY_CYCLE_16;
}
/**
* @brief sdram command confg
* @param xmc_sdram_cmd_struct: pointer to a xmc_sdram_cmd_type
* structure which will be initialized.
* @retval none
*/
void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
{
XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
(xmc_sdram_cmd_struct->data << 9) |
xmc_sdram_cmd_struct->cmd |
xmc_sdram_cmd_struct->cmd_banks;
}
/**
* @brief get sdram bank status
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_SDRAM_BANK1
* - XMC_SDRAM_BANK1
* @retval the bank status
*/
uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
{
if(xmc_bank == XMC_SDRAM_BANK1)
{
return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
}
else
{
return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
}
}
/**
* @brief set sdram refresh counter
* @param counter: xmc sdram refresh counter
* @retval none
*/
void xmc_sdram_refresh_counter_set(uint32_t counter)
{
XMC_SDRAM->rcnt_bit.rc = counter;
}
/**
* @brief set sdram auto refresh number
* @param number: xmc sdram auto refresh number
* @retval none
*/
void xmc_sdram_auto_refresh_set(uint32_t number)
{
XMC_SDRAM->cmd_bit.art = number;
}
/**
* @brief enable or disable the specified xmc interrupts.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* - XMC_BANK5_6_SDRAM
* @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - XMC_INT_RISING_EDGE
* - XMC_INT_LEVEL
* - XMC_INT_FALLING_EDGE
* - XMC_INT_ERR
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
{
if(new_state != FALSE)
{
/* enable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2is |= xmc_int;
}
/* enable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3is |= xmc_int;
}
/* enable the selected xmc_bank4 interrupts */
else if(xmc_bank == XMC_BANK4_PCCARD)
{
XMC_BANK4->bk4is |= xmc_int;
}
/* enable the selected xmc_sdram interrupts */
else
{
XMC_SDRAM->rcnt |= xmc_int;
}
}
else
{
/* disable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2is &= ~xmc_int;
}
/* disable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3is &= ~xmc_int;
}
/* disable the selected xmc_bank4 interrupts */
else if(xmc_bank == XMC_BANK4_PCCARD)
{
XMC_BANK4->bk4is &= ~xmc_int;
}
/* disable the selected xmc_sdram interrupts */
else
{
XMC_SDRAM->rcnt &= ~xmc_int;
}
}
}
/**
* @brief check whether the specified xmc flag is set or not.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* - XMC_BANK5_6_SDRAM
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* - XMC_FEMPT_FLAG
* - XMC_BUSY_FLAG
* - XMC_ERR_FLAG
* @retval none
*/
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(xmc_bank == XMC_BANK2_NAND)
{
temp = XMC_BANK2->bk2is;
}
else if(xmc_bank == XMC_BANK3_NAND)
{
temp = XMC_BANK3->bk3is;
}
else if(xmc_bank == XMC_BANK4_PCCARD)
{
temp = XMC_BANK4->bk4is;
}
else
{
temp = XMC_SDRAM->sts;
}
/* get the flag status */
if((temp & xmc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
/* return the flag status */
return status;
}
/**
* @brief clear the xmc's pending flags.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* - XMC_BANK3_NAND
* - XMC_BANK4_PCCARD
* - XMC_BANK5_6_SDRAM
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* - XMC_ERR_FLAG
* @retval none
*/
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
__IO uint32_t int_state;
if(xmc_bank == XMC_BANK2_NAND)
{
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK3_NAND)
{
int_state = XMC_BANK3->bk3is & 0x38; /* keep interrupt state */
XMC_BANK3->bk3is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK4_PCCARD)
{
int_state = XMC_BANK4->bk4is & 0x38; /* keep interrupt state */
XMC_BANK4->bk4is = (~(xmc_flag | 0x38) | int_state);
}
else
{
XMC_SDRAM->rcnt |= xmc_flag;
}
}
/**
* @brief xmc pc card registers reset
* @param none
* @retval none
*/
void xmc_pccard_reset(void)
{
/* Set the XMC_Bank4 registers to their reset values */
XMC_BANK4->bk4ctrl = 0x00000018;
XMC_BANK4->bk4is = 0x00000000;
XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_pccard_init_struct.
* @param xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
XMC_BUSTYPE_16_BITS |
(xmc_pccard_init_struct->delay_time_cr << 9) |
(xmc_pccard_init_struct->delay_time_ar << 13);
}
/**
* @brief initialize the xmc pccard bank according to the specified
* parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
/* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
(xmc_special_spacetiming_struct->mem_waite_time << 8) |
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
(xmc_iospace_timing_struct->mem_waite_time << 8) |
(xmc_iospace_timing_struct->mem_hold_time << 16) |
(xmc_iospace_timing_struct->mem_hiz_time << 24);
}
/**
* @brief fill each xmc_pccard_init_struct member with its default value.
* @param xmc_pccard_init_struct: pointer to a xmc_pccardinittype
* structure which will be initialized.
* @retval none
*/
void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
{
/* reset pccard init structure parameters values */
xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
xmc_pccard_init_struct->delay_time_ar = 0x0;
xmc_pccard_init_struct->delay_time_cr = 0x0;
}
/**
* @brief fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
* and xmc_iospace_timing_struct member with its default value.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
* structure that contains the configuration information for the xmc
* pccard bank.
* @retval none
*/
void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
xmc_regular_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_iospace_timing_struct->class_bank = XMC_BANK4_PCCARD;
xmc_iospace_timing_struct->mem_hold_time = 0xFC;
xmc_iospace_timing_struct->mem_waite_time = 0xFC;
xmc_iospace_timing_struct->mem_setup_time = 0xFC;
xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
}
/**
* @brief enable or disable the pccard memory bank.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_pccard_enable(confirm_state new_state)
{
/* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
XMC_BANK4->bk4ctrl_bit.en = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __AT32F435_437_H
#define __AT32F435_437_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F435_437
* @{
*/
/** @addtogroup Library_configuration_section
* @{
*/
/**
* tip: to avoid modifying this file each time you need to switch between these
* devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (AT32F435CCU7) && !defined (AT32F435CGU7) && !defined (AT32F435CMU7) && \
!defined (AT32F435CCT7) && !defined (AT32F435CGT7) && !defined (AT32F435CMT7) && \
!defined (AT32F435RCT7) && !defined (AT32F435RGT7) && !defined (AT32F435RMT7) && \
!defined (AT32F435VCT7) && !defined (AT32F435VGT7) && !defined (AT32F435VMT7) && \
!defined (AT32F435ZCT7) && !defined (AT32F435ZGT7) && !defined (AT32F435ZMT7) && \
!defined (AT32F437RCT7) && !defined (AT32F437RGT7) && !defined (AT32F437RMT7) && \
!defined (AT32F437VCT7) && !defined (AT32F437VGT7) && !defined (AT32F437VMT7) && \
!defined (AT32F437ZCT7) && !defined (AT32F437ZGT7) && !defined (AT32F437ZMT7)
#error "Please select first the target device used in your application (in at32f435_437.h file)"
#endif
#if defined (AT32F435CCU7) || defined (AT32F435CGU7) || defined (AT32F435CMU7) || \
defined (AT32F435CCT7) || defined (AT32F435CGT7) || defined (AT32F435CMT7) || \
defined (AT32F435RCT7) || defined (AT32F435RGT7) || defined (AT32F435RMT7) || \
defined (AT32F435VCT7) || defined (AT32F435VGT7) || defined (AT32F435VMT7) || \
defined (AT32F435ZCT7) || defined (AT32F435ZGT7) || defined (AT32F435ZMT7)
#define AT32F435xx
//#define AT32F43x
#endif
#if defined (AT32F437RCT7) || defined (AT32F437RGT7) || defined (AT32F437RMT7) || \
defined (AT32F437VCT7) || defined (AT32F437VGT7) || defined (AT32F437VMT7) || \
defined (AT32F437ZCT7) || defined (AT32F437ZGT7) || defined (AT32F437ZMT7)
#define AT32F437xx
//#define AT32F43x
#endif
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
*/
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
#define USE_STDPERIPH_DRIVER
#endif
#endif
#endif
/**
* @brief at32f435_437 standard peripheral library version number
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
(__AT32F435_437_LIBRARY_VERSION_MINOR << 8) | \
(__AT32F435_437_LIBRARY_VERSION_RC))
/**
* @}
*/
/** @addtogroup configuration_section_for_cmsis
* @{
*/
/**
* @brief configuration of the cortex-m4 processor and core peripherals
*/
#define __CM4_REV 0x0001U /*!< core revision r0p1 */
#define __MPU_PRESENT 1 /*!< mpu present */
#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
//#define __FPU_PRESENT 1U /*!< fpu present */
/**
* @brief at32f435_437 interrupt number definition, according to the selected device
* in @ref library_configuration_section
*/
typedef enum IRQn
{
/****** cortex-m4 processor exceptions numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
/****** at32 specific interrupt numbers *********************************************************/
WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */
ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */
FLASH_IRQn = 4, /*!< flash global interrupt */
CRM_IRQn = 5, /*!< crm global interrupt */
EXINT0_IRQn = 6, /*!< exint line0 interrupt */
EXINT1_IRQn = 7, /*!< exint line1 interrupt */
EXINT2_IRQn = 8, /*!< exint line2 interrupt */
EXINT3_IRQn = 9, /*!< exint line3 interrupt */
EXINT4_IRQn = 10, /*!< exint line4 interrupt */
EDMA_Stream1_IRQn = 11, /*!< edma stream 1 global interrupt */
EDMA_Stream2_IRQn = 12, /*!< edma stream 2 global interrupt */
EDMA_Stream3_IRQn = 13, /*!< edma stream 3 global interrupt */
EDMA_Stream4_IRQn = 14, /*!< edma stream 4 global interrupt */
EDMA_Stream5_IRQn = 15, /*!< edma stream 5 global interrupt */
EDMA_Stream6_IRQn = 16, /*!< edma stream 6 global interrupt */
EDMA_Stream7_IRQn = 17, /*!< edma stream 7 global interrupt */
#if defined (AT32F435xx)
ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
SPI1_IRQn = 35, /*!< spi1 global interrupt */
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
USART1_IRQn = 37, /*!< usart1 global interrupt */
USART2_IRQn = 38, /*!< usart2 global interrupt */
USART3_IRQn = 39, /*!< usart3 global interrupt */
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
EDMA_Stream8_IRQn = 47, /*!< edma stream 8 global interrupt */
XMC_IRQn = 48, /*!< xmc global interrupt */
SDIO1_IRQn = 49, /*!< sdio global interrupt */
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
UART4_IRQn = 52, /*!< uart4 global interrupt */
UART5_IRQn = 53, /*!< uart5 global interrupt */
TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
USART6_IRQn = 71, /*!< usart6 interrupt */
I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
DVP_IRQn = 78, /*!< dvp interrupt */
FPU_IRQn = 81, /*!< fpu interrupt */
UART7_IRQn = 82, /*!< uart7 interrupt */
UART8_IRQn = 83, /*!< uart8 interrupt */
SPI4_IRQn = 84, /*!< spi4 global interrupt */
QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
ACC_IRQn = 103, /*!< acc interrupt */
TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
DMA2_Channel1_IRQn = 108, /*!< dma2 channel 1 global interrupt */
DMA2_Channel2_IRQn = 109, /*!< dma2 channel 2 global interrupt */
DMA2_Channel3_IRQn = 110, /*!< dma2 channel 3 global interrupt */
DMA2_Channel4_IRQn = 111, /*!< dma2 channel 4 global interrupt */
DMA2_Channel5_IRQn = 112, /*!< dma2 channel 5 global interrupt */
DMA2_Channel6_IRQn = 113, /*!< dma2 channel 6 global interrupt */
DMA2_Channel7_IRQn = 114, /*!< dma2 channel 7 global interrupt */
#endif
#if defined (AT32F437xx)
ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
SPI1_IRQn = 35, /*!< spi1 global interrupt */
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
USART1_IRQn = 37, /*!< usart1 global interrupt */
USART2_IRQn = 38, /*!< usart2 global interrupt */
USART3_IRQn = 39, /*!< usart3 global interrupt */
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
EDMA_Stream8_IRQn = 47, /*!< dma1 stream 8 global interrupt */
XMC_IRQn = 48, /*!< xmc global interrupt */
SDIO1_IRQn = 49, /*!< sdio global interrupt */
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
UART4_IRQn = 52, /*!< uart4 global interrupt */
UART5_IRQn = 53, /*!< uart5 global interrupt */
TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
EMAC_IRQn = 61, /*!< emac interrupt */
EMAC_WKUP_IRQn = 62, /*!< emac wakeup interrupt */
CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
USART6_IRQn = 71, /*!< usart6 interrupt */
I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
DVP_IRQn = 78, /*!< dvp interrupt */
FPU_IRQn = 81, /*!< fpu interrupt */
UART7_IRQn = 82, /*!< uart7 interrupt */
UART8_IRQn = 83, /*!< uart8 interrupt */
SPI4_IRQn = 84, /*!< spi4 global interrupt */
QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
ACC_IRQn = 103, /*!< acc interrupt */
TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
DMA2_Channel1_IRQn = 108, /*!< dma2 channel 1 global interrupt */
DMA2_Channel2_IRQn = 109, /*!< dma2 channel 2 global interrupt */
DMA2_Channel3_IRQn = 110, /*!< dma2 channel 3 global interrupt */
DMA2_Channel4_IRQn = 111, /*!< dma2 channel 4 global interrupt */
DMA2_Channel5_IRQn = 112, /*!< dma2 channel 5 global interrupt */
DMA2_Channel6_IRQn = 113, /*!< dma2 channel 6 global interrupt */
DMA2_Channel7_IRQn = 114, /*!< dma2 channel 7 global interrupt */
#endif
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h"
#include "system_at32f435_437.h"
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
typedef int32_t INT32;
typedef int16_t INT16;
typedef int8_t INT8;
typedef uint32_t UINT32;
typedef uint16_t UINT16;
typedef uint8_t UINT8;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< read only */
typedef const int16_t sc16; /*!< read only */
typedef const int8_t sc8; /*!< read only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< read only */
typedef __I int16_t vsc16; /*!< read only */
typedef __I int8_t vsc8; /*!< read only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< read only */
typedef const uint16_t uc16; /*!< read only */
typedef const uint8_t uc8; /*!< read only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< read only */
typedef __I uint16_t vuc16; /*!< read only */
typedef __I uint8_t vuc8; /*!< read only */
typedef enum {RESET = 0, SET = !RESET} flag_status;
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define REG8(addr) *(volatile uint8_t *)(addr)
#define REG16(addr) *(volatile uint16_t *)(addr)
#define REG32(addr) *(volatile uint32_t *)(addr)
#define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f))
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
#define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f))
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define XMC_SDRAM_MEM_BASE ((uint32_t)0xC0000000)
#define QSPI2_MEM_BASE ((uint32_t)0xB0000000)
#define XMC_CARD_MEM_BASE ((uint32_t)0xA8000000)
#define QSPI2_REG_BASE ((uint32_t)0xA0002000)
#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
#define XMC_REG_BASE ((uint32_t)0xA0000000)
#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
#define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
#define QSPI1_MEM_BASE ((uint32_t)0x90000000)
#define XMC_MEM_BASE ((uint32_t)0x60000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define SRAM_BB_BASE ((uint32_t)0x22000000)
#define PERIPH_BB_BASE ((uint32_t)0x42000000)
#define SRAM_BASE ((uint32_t)0x20000000)
#define USD_BASE ((uint32_t)0x1FFFC000)
#define FLASH_BASE ((uint32_t)0x08000000)
#define DEBUG_BASE ((uint32_t)0xE0042000)
#define APB1PERIPH_BASE (PERIPH_BASE)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
#define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000)
#if defined (AT32F435xx)
/* apb1 bus base address */
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
/* apb2 bus base address */
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
/* ahb bus base address */
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
#endif
#if defined (AT32F437xx)
/* apb1 bus base address */
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
/* apb2 bus base address */
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
/* ahb bus base address */
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
#define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
#define EMAC_MAC_BASE (EMAC_BASE)
#define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
#define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
#define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#include "at32f435_437_def.h"
#include "at32f435_437_conf.h"
#ifdef __cplusplus
}
#endif
#endif

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lib/main/AT32F43x/Drivers/CMSIS/Device/ST/AT32F43x/at32f435_437_clock.c Normal file
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/**
**************************************************************************
* @file at32f435_437_clock.c
* @version v2.1.0
* @date 2022-08-16
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f435_437_clock.h"
/** @addtogroup AT32F437_periph_template
* @{
*/
/** @addtogroup 437_System_clock_configuration System_clock_configuration
* @{
*/
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = (hext * pll_ns)/(pll_ms * pll_fr)
* - system clock source = pll (hext)
* - hext = 8000000
* - sclk = 288000000
* - ahbdiv = 1
* - ahbclk = 288000000
* - apb2div = 2
* - apb2clk = 144000000
* - apb1div = 2
* - apb1clk = 144000000
* - pll_ns = 72
* - pll_ms = 1
* - pll_fr = 2
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
/* config ldo voltage */
pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource
common frequency config list: pll source selected hick or hext(8mhz)
_______________________________________________________________________________________
| | | | | | | | | |
|pll(mhz)| 288 | 252 | 216 | 180 | 144 | 108 | 72 | 36 |
|________|_________|_________|_________|_________|_________|_________|_________________|
| | | | | | | | | |
|pll_ns | 72 | 63 | 108 | 90 | 72 | 108 | 72 | 72 |
| | | | | | | | | |
|pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| | | | | | | | | |
|pll_fr | FR_2 | FR_2 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16|
|________|_________|_________|_________|_________|_________|_________|________|________|
if pll clock source selects hext with other frequency values, or configure pll to other
frequency values, please use the at32 new clock configuration tool for configuration. */
crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* config usbclk from pll */
crm_usb_clock_div_set(CRM_USB_DIV_6);
crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLL);
/* update system_core_clock global variable */
system_core_clock_update();
}
/**
* @}
*/
/**
* @}
*/

46
lib/main/AT32F43x/Drivers/CMSIS/Device/ST/AT32F43x/at32f435_437_clock.h Normal file
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/**
**************************************************************************
* @file at32f435_437_clock.h
* @version v2.1.0
* @date 2022-08-16
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CLOCK_H
#define __AT32F435_437_CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/* exported functions ------------------------------------------------------- */
void system_clock_config(void);
#ifdef __cplusplus
}
#endif
#endif

249
lib/main/AT32F43x/Drivers/CMSIS/Device/ST/AT32F43x/at32f435_437_conf.h Normal file
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/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CONF_H
#define __AT32F435_437_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef NULL
#ifdef __cplusplus
#define NULL 0
#else
#define NULL ((void *) 0)
#endif
#endif
/** @addtogroup AT32F437_periph_template
* @{
*/
/** @addtogroup 437_Library_configuration Library_configuration
* @{
*/
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)
* used in your application
*
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define DAC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define EDMA_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define SDIO_MODULE_ENABLED
#define XMC_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define ACC_MODULE_ENABLED
#define MISC_MODULE_ENABLED
#define QSPI_MODULE_ENABLED
#define DVP_MODULE_ENABLED
#define SCFG_MODULE_ENABLED
#define EMAC_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f435_437_crm.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f435_437_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f435_437_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f435_437_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f435_437_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f435_437_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f435_437_pwc.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f435_437_can.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f435_437_adc.h"
#endif
#ifdef DAC_MODULE_ENABLED
#include "at32f435_437_dac.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f435_437_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f435_437_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f435_437_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f435_437_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f435_437_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f435_437_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f435_437_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f435_437_exint.h"
#endif
#ifdef SDIO_MODULE_ENABLED
#include "at32f435_437_sdio.h"
#endif
#ifdef XMC_MODULE_ENABLED
#include "at32f435_437_xmc.h"
#endif
#ifdef ACC_MODULE_ENABLED
#include "at32f435_437_acc.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f435_437_misc.h"
#endif
#ifdef EDMA_MODULE_ENABLED
#include "at32f435_437_edma.h"
#endif
#ifdef QSPI_MODULE_ENABLED
#include "at32f435_437_qspi.h"
#endif
#ifdef SCFG_MODULE_ENABLED
#include "at32f435_437_scfg.h"
#endif
#ifdef EMAC_MODULE_ENABLED
#include "at32f435_437_emac.h"
#endif
#ifdef DVP_MODULE_ENABLED
#include "at32f435_437_dvp.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f435_437_usb.h"
#endif
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
/* Double Precision Float CFFT twiddles */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
extern const uint16_t armBitRevTable[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
extern const uint64_t twiddleCoefF64_16[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
extern const uint64_t twiddleCoefF64_32[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
extern const uint64_t twiddleCoefF64_64[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
extern const uint64_t twiddleCoefF64_128[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
extern const uint64_t twiddleCoefF64_256[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
extern const uint64_t twiddleCoefF64_512[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
extern const uint64_t twiddleCoefF64_1024[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
extern const uint64_t twiddleCoefF64_2048[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
extern const uint64_t twiddleCoefF64_4096[8192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
extern const float32_t twiddleCoef_16[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
extern const float32_t twiddleCoef_32[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
extern const float32_t twiddleCoef_64[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
extern const float32_t twiddleCoef_128[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
extern const float32_t twiddleCoef_256[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
extern const float32_t twiddleCoef_512[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
extern const float32_t twiddleCoef_1024[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
extern const float32_t twiddleCoef_2048[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
extern const q31_t twiddleCoef_16_q31[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
extern const q31_t twiddleCoef_32_q31[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
extern const q31_t twiddleCoef_64_q31[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
extern const q31_t twiddleCoef_128_q31[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
extern const q31_t twiddleCoef_256_q31[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
extern const q31_t twiddleCoef_512_q31[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
extern const q31_t twiddleCoef_1024_q31[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
extern const q31_t twiddleCoef_2048_q31[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
extern const q31_t twiddleCoef_4096_q31[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
extern const q15_t twiddleCoef_16_q15[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
extern const q15_t twiddleCoef_32_q15[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
extern const q15_t twiddleCoef_64_q15[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
extern const q15_t twiddleCoef_128_q15[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
extern const q15_t twiddleCoef_256_q15[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
extern const q15_t twiddleCoef_512_q15[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
extern const q15_t twiddleCoef_1024_q15[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
extern const q15_t twiddleCoef_2048_q15[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
extern const q15_t twiddleCoef_4096_q15[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* Double Precision Float RFFT twiddles */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
extern const uint64_t twiddleCoefF64_rfft_32[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
extern const uint64_t twiddleCoefF64_rfft_64[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
extern const uint64_t twiddleCoefF64_rfft_128[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
extern const uint64_t twiddleCoefF64_rfft_256[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
extern const uint64_t twiddleCoefF64_rfft_512[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
extern const float32_t twiddleCoef_rfft_32[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
extern const float32_t twiddleCoef_rfft_64[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
extern const float32_t twiddleCoef_rfft_128[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
extern const float32_t twiddleCoef_rfft_256[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
extern const float32_t twiddleCoef_rfft_512[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
extern const float32_t twiddleCoef_rfft_1024[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
extern const float32_t twiddleCoef_rfft_2048[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
extern const float32_t twiddleCoef_rfft_4096[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* Double precision floating-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* floating-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* fixed-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
extern const float32_t realCoefA[8192];
extern const float32_t realCoefB[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
extern const q31_t realCoefAQ31[8192];
extern const q31_t realCoefBQ31[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
extern const q15_t realCoefAQ15[8192];
extern const q15_t realCoefBQ15[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
extern const float32_t Weights_128[256];
extern const float32_t cos_factors_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
extern const float32_t Weights_512[1024];
extern const float32_t cos_factors_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
extern const float32_t Weights_2048[4096];
extern const float32_t cos_factors_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
extern const float32_t Weights_8192[16384];
extern const float32_t cos_factors_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
extern const q15_t WeightsQ15_128[256];
extern const q15_t cos_factorsQ15_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
extern const q15_t WeightsQ15_512[1024];
extern const q15_t cos_factorsQ15_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
extern const q15_t WeightsQ15_2048[4096];
extern const q15_t cos_factorsQ15_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
extern const q15_t WeightsQ15_8192[16384];
extern const q15_t cos_factorsQ15_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
extern const q31_t WeightsQ31_128[256];
extern const q31_t cos_factorsQ31_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
extern const q31_t WeightsQ31_512[1024];
extern const q31_t cos_factorsQ31_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
extern const q31_t WeightsQ31_2048[4096];
extern const q31_t cos_factorsQ31_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
extern const q31_t WeightsQ31_8192[16384];
extern const q31_t cos_factorsQ31_8192[8192];
#endif
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
extern const q15_t armRecipTableQ15[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
extern const q31_t armRecipTableQ31[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
/* Tables for Fast Math Sine and Cosine */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if defined(ARM_MATH_MVEI)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
extern const q31_t sqrtTable_Q31[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#endif
#if defined(ARM_MATH_MVEI)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
extern const q15_t sqrtTable_Q15[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#endif
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
extern const float32_t exp_tab[8];
extern const float32_t __logf_lut_f32[8];
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
extern const unsigned char hwLUT[256];
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_helium_utils.h
* Description: Utility functions for Helium development
*
* $Date: 09. September 2019
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_UTILS_HELIUM_H_
#define _ARM_UTILS_HELIUM_H_
/***************************************
Definitions available for MVEF and MVEI
***************************************/
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
#define INACTIVELANE 0 /* inactive lane content */
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
/***************************************
Definitions available for MVEF only
***************************************/
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
{
float32_t acc;
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
vgetq_lane(in, 2) + vgetq_lane(in, 3);
return acc;
}
/* newton initial guess */
#define INVSQRT_MAGIC_F32 0x5f3759df
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
{ \
float32x4_t tmp; \
\
/* tmp = xhalf * x * x */ \
tmp = vmulq(xStart, xStart); \
tmp = vmulq(tmp, xHalf); \
/* (1.5f - xhalf * x * x) */ \
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
/* x = x*(1.5f-xhalf*x*x); */ \
invSqrt = vmulq(tmp, xStart); \
}
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
/***************************************
Definitions available for MVEI only
***************************************/
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)
#include "arm_common_tables.h"
/* Following functions are used to transpose matrix in f32 and q31 cases */
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
uint32_t * pDataSrc,
uint32_t * pDataDest)
{
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
/*
*
* | 0 1 | => | 0 2 |
* | 2 3 | | 1 3 |
*
*/
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
uint32_t * pDataSrc,
uint32_t * pDataDest)
{
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
/*
*
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
*
*/
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
pDataDest[8] = pDataSrc[8];
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
{
/*
* 4x4 Matrix transposition
* is 4 x de-interleave operation
*
* 0 1 2 3 0 4 8 12
* 4 5 6 7 1 5 9 13
* 8 9 10 11 2 6 10 14
* 12 13 14 15 3 7 11 15
*/
uint32x4x4_t vecIn;
vecIn = vld4q((uint32_t const *) pDataSrc);
vstrwq(pDataDest, vecIn.val[0]);
pDataDest += 4;
vstrwq(pDataDest, vecIn.val[1]);
pDataDest += 4;
vstrwq(pDataDest, vecIn.val[2]);
pDataDest += 4;
vstrwq(pDataDest, vecIn.val[3]);
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
uint16_t srcRows,
uint16_t srcCols,
uint32_t * pDataSrc,
uint32_t * pDataDest)
{
uint32x4_t vecOffs;
uint32_t i;
uint32_t blkCnt;
uint32_t const *pDataC;
uint32_t *pDataDestR;
uint32x4_t vecIn;
vecOffs = vidupq_u32((uint32_t)0, 1);
vecOffs = vecOffs * srcCols;
i = srcCols;
do
{
pDataC = (uint32_t const *) pDataSrc;
pDataDestR = pDataDest;
blkCnt = srcRows >> 2;
while (blkCnt > 0U)
{
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
vstrwq(pDataDestR, vecIn);
pDataDestR += 4;
pDataC = pDataC + srcCols * 4;
/*
* Decrement the blockSize loop counter
*/
blkCnt--;
}
/*
* tail
*/
blkCnt = srcRows & 3;
if (blkCnt > 0U)
{
mve_pred16_t p0 = vctp32q(blkCnt);
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
vstrwq_p(pDataDestR, vecIn, p0);
}
pDataSrc += 1;
pDataDest += srcRows;
}
while (--i);
return (ARM_MATH_SUCCESS);
}
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
{
q63x2_t vecTmpLL;
q31x4_t vecTmp0, vecTmp1;
q31_t scale;
q63_t tmp64;
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
vecSignBits = vclsq(vecIn);
vecSignBits = vbicq(vecSignBits, 1);
/*
* in = in << no_of_sign_bits;
*/
vecNrm = vshlq(vecIn, vecSignBits);
/*
* index = in >> 24;
*/
vecIdx = vecNrm >> 24;
vecIdx = vecIdx << 1;
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
vecIdx = vecIdx + 1;
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
vecTmp0 = vecTmp0 - vecTmp1;
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
/*
* scale elements 0, 2
*/
scale = 26 + (vecSignBits[0] >> 1);
tmp64 = asrl(vecTmpLL[0], scale);
vecDst[0] = (q31_t) tmp64;
scale = 26 + (vecSignBits[2] >> 1);
tmp64 = asrl(vecTmpLL[1], scale);
vecDst[2] = (q31_t) tmp64;
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
/*
* scale elements 1, 3
*/
scale = 26 + (vecSignBits[1] >> 1);
tmp64 = asrl(vecTmpLL[0], scale);
vecDst[1] = (q31_t) tmp64;
scale = 26 + (vecSignBits[3] >> 1);
tmp64 = asrl(vecTmpLL[1], scale);
vecDst[3] = (q31_t) tmp64;
/*
* set negative values to 0
*/
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
return vecDst;
}
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
{
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
q15x8_t vecTmp0, vecTmp1;
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
vecDst = vuninitializedq_s16();
vecSignBits = vclsq(vecIn);
vecSignBits = vbicq(vecSignBits, 1);
/*
* in = in << no_of_sign_bits;
*/
vecNrm = vshlq(vecIn, vecSignBits);
vecIdx = vecNrm >> 8;
vecIdx = vecIdx << 1;
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
vecIdx = vecIdx + 1;
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
vecTmp0 = vecTmp0 - vecTmp1;
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
vecSignBits = vecSignBits >> 1;
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
vecTmp0 = vecSignBits + 10;
/*
* negate sign to apply register based vshl
*/
vecTmp0 = -vecTmp0;
/*
* shift even elements
*/
vecSignL = vmovlbq(vecTmp0);
vecTmpLev = vshlq(vecTmpLev, vecSignL);
/*
* shift odd elements
*/
vecSignL = vmovltq(vecTmp0);
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
/*
* merge and narrow odd and even parts
*/
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
/*
* set negative values to 0
*/
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
return vecDst;
}
#endif
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
#endif

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_mve_tables.h
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
* used for MVE implementation only
*
* $Date: 08. January 2020
* $Revision: V1.7.0
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_MVE_TABLES_H
#define _ARM_MVE_TABLES_H
#include "arm_math.h"
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
extern float32_t rearranged_twiddle_stride1_16_f32[8];
extern float32_t rearranged_twiddle_stride2_16_f32[8];
extern float32_t rearranged_twiddle_stride3_16_f32[8];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
extern float32_t rearranged_twiddle_stride1_64_f32[40];
extern float32_t rearranged_twiddle_stride2_64_f32[40];
extern float32_t rearranged_twiddle_stride3_64_f32[40];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
extern float32_t rearranged_twiddle_stride1_256_f32[168];
extern float32_t rearranged_twiddle_stride2_256_f32[168];
extern float32_t rearranged_twiddle_stride3_256_f32[168];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
extern float32_t rearranged_twiddle_stride1_1024_f32[680];
extern float32_t rearranged_twiddle_stride2_1024_f32[680];
extern float32_t rearranged_twiddle_stride3_1024_f32[680];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
#endif
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
#if defined(ARM_MATH_MVEI)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
extern q31_t rearranged_twiddle_stride1_16_q31[8];
extern q31_t rearranged_twiddle_stride2_16_q31[8];
extern q31_t rearranged_twiddle_stride3_16_q31[8];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
extern q31_t rearranged_twiddle_stride1_64_q31[40];
extern q31_t rearranged_twiddle_stride2_64_q31[40];
extern q31_t rearranged_twiddle_stride3_64_q31[40];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
extern q31_t rearranged_twiddle_stride1_256_q31[168];
extern q31_t rearranged_twiddle_stride2_256_q31[168];
extern q31_t rearranged_twiddle_stride3_256_q31[168];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
extern q31_t rearranged_twiddle_stride1_1024_q31[680];
extern q31_t rearranged_twiddle_stride2_1024_q31[680];
extern q31_t rearranged_twiddle_stride3_1024_q31[680];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
#endif
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
#endif /* defined(ARM_MATH_MVEI) */
#if defined(ARM_MATH_MVEI)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
extern q15_t rearranged_twiddle_stride1_16_q15[8];
extern q15_t rearranged_twiddle_stride2_16_q15[8];
extern q15_t rearranged_twiddle_stride3_16_q15[8];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
extern q15_t rearranged_twiddle_stride1_64_q15[40];
extern q15_t rearranged_twiddle_stride2_64_q15[40];
extern q15_t rearranged_twiddle_stride3_64_q15[40];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
extern q15_t rearranged_twiddle_stride1_256_q15[168];
extern q15_t rearranged_twiddle_stride2_256_q15[168];
extern q15_t rearranged_twiddle_stride3_256_q15[168];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
extern q15_t rearranged_twiddle_stride1_1024_q15[680];
extern q15_t rearranged_twiddle_stride2_1024_q15[680];
extern q15_t rearranged_twiddle_stride3_1024_q15[680];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
#endif
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
#endif /* defined(ARM_MATH_MVEI) */
#if defined(ARM_MATH_MVEI)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
#endif /* defined(ARM_MATH_MVEI) */
#endif /*_ARM_MVE_TABLES_H*/

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/******************************************************************************
* @file arm_vec_math.h
* @brief Public header file for CMSIS DSP Library
* @version V1.7.0
* @date 15. October 2019
******************************************************************************/
/*
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_VEC_MATH_H
#define _ARM_VEC_MATH_H
#include "arm_math.h"
#include "arm_common_tables.h"
#include "arm_helium_utils.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
#define INV_NEWTON_INIT_F32 0x7EF127EA
static const float32_t __logf_rng_f32=0.693147180f;
/* fast inverse approximation (3x newton) */
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
f32x4_t x)
{
q31x4_t m;
f32x4_t b;
any32x4_t xinv;
f32x4_t ax = vabsq(x);
xinv.f = ax;
m = 0x3F800000 - (xinv.i & 0x7F800000);
xinv.i = xinv.i + m;
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
xinv.i = xinv.i + m;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
/*
* restore sign
*/
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
return xinv.f;
}
/* fast inverse approximation (4x newton) */
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
f32x4_t x)
{
q31x4_t m;
f32x4_t b;
any32x4_t xinv;
f32x4_t ax = vabsq(x);
xinv.f = ax;
m = 0x3F800000 - (xinv.i & 0x7F800000);
xinv.i = xinv.i + m;
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
xinv.i = xinv.i + m;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
b = 2.0f - xinv.f * ax;
xinv.f = xinv.f * b;
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
/*
* restore sign
*/
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
return xinv.f;
}
__STATIC_INLINE f32x4_t vdiv_f32(
f32x4_t num, f32x4_t den)
{
return vmulq(num, vrecip_hiprec_f32(den));
}
/**
@brief Single-precision taylor dev.
@param[in] x f32 quad vector input
@param[in] coeffs f32 quad vector coeffs
@return destination f32 quad vector
*/
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
f32x4_t x,
const float32_t * coeffs)
{
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
f32x4_t x2 = vmulq(x, x);
f32x4_t x4 = vmulq(x2, x2);
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
return res;
}
__STATIC_INLINE f32x4_t vmant_exp_f32(
f32x4_t x,
int32x4_t * e)
{
any32x4_t r;
int32x4_t n;
r.f = x;
n = r.i >> 23;
n = n - 127;
r.i = r.i - (n << 23);
*e = n;
return r.f;
}
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
{
q31x4_t vecExpUnBiased;
f32x4_t vecTmpFlt0, vecTmpFlt1;
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
f32x4_t vecExpUnBiasedFlt;
/*
* extract exponent
*/
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
/*
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
*/
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
/*
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
*/
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
/*
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
*/
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
/*
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
*/
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
/*
* a = a + b * xx;
*/
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
/*
* c = c + d * xx;
*/
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
/*
* xx = xx * xx;
*/
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
/*
* r.f = a + c * xx;
*/
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
/*
* add exponent
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
*/
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
// set log0 down to -inf
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
return vecAcc0;
}
__STATIC_INLINE f32x4_t vexpq_f32(
f32x4_t x)
{
// Perform range reduction [-log(2),log(2)]
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
// Polynomial Approximation
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
// Reconstruct
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
return poly;
}
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
{
f32x4_t r = x;
nb--;
while (nb > 0) {
r = vmulq(r, x);
nb--;
}
return (r);
}
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
{
f32x4_t vecSx, vecW, vecTmp;
any32x4_t v;
vecSx = vabsq(vecIn);
v.f = vecIn;
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
vecW = vmulq(vecSx, v.f);
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
v.f = vmulq(v.f, vecTmp);
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
/*
* restore sign
*/
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
return v.f;
}
__STATIC_INLINE f32x4_t vtanhq_f32(
f32x4_t val)
{
f32x4_t x =
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
return tanh;
}
__STATIC_INLINE f32x4_t vpowq_f32(
f32x4_t val,
f32x4_t n)
{
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
}
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
#include "NEMath.h"
/**
* @brief Vectorized integer exponentiation
* @param[in] x value
* @param[in] nb integer exponent >= 1
* @return x^nb
*
*/
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
{
float32x4_t r = x;
nb --;
while(nb > 0)
{
r = vmulq_f32(r , x);
nb--;
}
return(r);
}
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
{
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
float32x4_t e = vrsqrteq_f32(x1);
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
return vmulq_f32(x, e);
}
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
{
float32x4_t tempF;
int32x4_t tempHI,tempLO;
tempLO = vmovl_s16(vget_low_s16(vec));
tempF = vcvtq_n_f32_s32(tempLO,15);
tempF = __arm_vec_sqrt_f32_neon(tempF);
tempLO = vcvtq_n_s32_f32(tempF,15);
tempHI = vmovl_s16(vget_high_s16(vec));
tempF = vcvtq_n_f32_s32(tempHI,15);
tempF = __arm_vec_sqrt_f32_neon(tempF);
tempHI = vcvtq_n_s32_f32(tempF,15);
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
}
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
{
float32x4_t temp;
temp = vcvtq_n_f32_s32(vec,31);
temp = __arm_vec_sqrt_f32_neon(temp);
return(vcvtq_n_s32_f32(temp,31));
}
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
#ifdef __cplusplus
}
#endif
#endif /* _ARM_VEC_MATH_H */
/**
*
* End of file.
*/

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/******************************************************************************
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.2.1
* @date 26. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/******************************************************************************
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/******************************************************************************
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.2.0
* @date 28. January 2020
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* __CMSIS_ICCARM_H__ */

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/******************************************************************************
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.1
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
* @version V1.0.0
* @date 24. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif

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lib/main/AT32F43x/Middlewares/AT/AT32_USB_Device_Library/Class/usbd_class/cdc/cdc_class.c Normal file
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/**
**************************************************************************
* @file cdc_class.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb cdc class type
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usbd_core.h"
#include "cdc_class.h"
#include "cdc_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_cdc_class
* @brief usb device class cdc demo
* @{
*/
/** @defgroup USB_cdc_class_private_functions
* @{
*/
static usb_sts_type class_init_handler(void *udev);
static usb_sts_type class_clear_handler(void *udev);
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup);
static usb_sts_type class_ept0_tx_handler(void *udev);
static usb_sts_type class_ept0_rx_handler(void *udev);
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_sof_handler(void *udev);
static usb_sts_type class_event_handler(void *udev, usbd_event_type event);
static usb_sts_type cdc_struct_init(cdc_struct_type *pcdc);
extern void usb_usart_config( linecoding_type linecoding);
static void usb_vcp_cmd_process(void *udev, uint8_t cmd, uint8_t *buff, uint16_t len);
linecoding_type linecoding =
{
115200,
0,
0,
8
};
/* cdc data struct */
cdc_struct_type cdc_struct;
/* usb device class handler */
usbd_class_handler cdc_class_handler =
{
class_init_handler,
class_clear_handler,
class_setup_handler,
class_ept0_tx_handler,
class_ept0_rx_handler,
class_in_handler,
class_out_handler,
class_sof_handler,
class_event_handler,
&cdc_struct
};
/**
* @brief initialize usb custom hid endpoint
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_init_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
/* init cdc struct */
cdc_struct_init(pcdc);
/* open in endpoint */
usbd_ept_open(pudev, USBD_CDC_INT_EPT, EPT_INT_TYPE, USBD_CDC_CMD_MAXPACKET_SIZE);
/* open in endpoint */
usbd_ept_open(pudev, USBD_CDC_BULK_IN_EPT, EPT_BULK_TYPE, USBD_CDC_IN_MAXPACKET_SIZE);
/* open out endpoint */
usbd_ept_open(pudev, USBD_CDC_BULK_OUT_EPT, EPT_BULK_TYPE, USBD_CDC_OUT_MAXPACKET_SIZE);
/* set out endpoint to receive status */
usbd_ept_recv(pudev, USBD_CDC_BULK_OUT_EPT, pcdc->g_rx_buff, USBD_CDC_OUT_MAXPACKET_SIZE);
return status;
}
/**
* @brief clear endpoint or other state
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_clear_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* close in endpoint */
usbd_ept_close(pudev, USBD_CDC_INT_EPT);
/* close in endpoint */
usbd_ept_close(pudev, USBD_CDC_BULK_IN_EPT);
/* close out endpoint */
usbd_ept_close(pudev, USBD_CDC_BULK_OUT_EPT);
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: to the structure of usbd_core_type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
{
/* class request */
case USB_REQ_TYPE_CLASS:
if(setup->wLength)
{
if(setup->bmRequestType & USB_REQ_DIR_DTH)
{
usb_vcp_cmd_process(udev, setup->bRequest, pcdc->g_cmd, setup->wLength);
usbd_ctrl_send(pudev, pcdc->g_cmd, setup->wLength);
}
else
{
pcdc->g_req = setup->bRequest;
pcdc->g_len = setup->wLength;
usbd_ctrl_recv(pudev, pcdc->g_cmd, pcdc->g_len);
}
}
break;
/* standard request */
case USB_REQ_TYPE_STANDARD:
switch(setup->bRequest)
{
case USB_STD_REQ_GET_DESCRIPTOR:
usbd_ctrl_unsupport(pudev);
break;
case USB_STD_REQ_GET_INTERFACE:
usbd_ctrl_send(pudev, (uint8_t *)&pcdc->alt_setting, 1);
break;
case USB_STD_REQ_SET_INTERFACE:
pcdc->alt_setting = setup->wValue;
break;
default:
break;
}
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
return status;
}
/**
* @brief usb device endpoint 0 in status stage complete
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_tx_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
UNUSED(udev);
return status;
}
/**
* @brief usb device endpoint 0 out status stage complete
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_rx_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
uint32_t recv_len = usbd_get_recv_len(pudev, 0);
/* ...user code... */
if( pcdc->g_req == SET_LINE_CODING)
{
/* class process */
usb_vcp_cmd_process(udev, pcdc->g_req, pcdc->g_cmd, recv_len);
}
return status;
}
/**
* @brief usb device transmision complete handler
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
usb_sts_type status = USB_OK;
/* ...user code...
trans next packet data
*/
usbd_flush_tx_fifo(pudev, ept_num);
pcdc->g_tx_completed = 1;
return status;
}
/**
* @brief usb device endpoint receive data
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
/* get endpoint receive data length */
pcdc->g_rxlen = usbd_get_recv_len(pudev, ept_num);
/*set recv flag*/
pcdc->g_rx_completed = 1;
return status;
}
/**
* @brief usb device sof handler
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_sof_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
UNUSED(udev);
return status;
}
/**
* @brief usb device event handler
* @param udev: to the structure of usbd_core_type
* @param event: usb device event
* @retval status of usb_sts_type
*/
static usb_sts_type class_event_handler(void *udev, usbd_event_type event)
{
usb_sts_type status = USB_OK;
UNUSED(udev);
switch(event)
{
case USBD_RESET_EVENT:
/* ...user code... */
break;
case USBD_SUSPEND_EVENT:
/* ...user code... */
break;
case USBD_WAKEUP_EVENT:
/* ...user code... */
break;
case USBD_INISOINCOM_EVENT:
break;
case USBD_OUTISOINCOM_EVENT:
break;
default:
break;
}
return status;
}
/**
* @brief usb device cdc init
* @param pcdc: to the structure of cdc_struct
* @retval status of usb_sts_type
*/
static usb_sts_type cdc_struct_init(cdc_struct_type *pcdc)
{
pcdc->g_tx_completed = 1;
pcdc->g_rx_completed = 0;
pcdc->alt_setting = 0;
pcdc->linecoding.bitrate = linecoding.bitrate;
pcdc->linecoding.data = linecoding.data;
pcdc->linecoding.format = linecoding.format;
pcdc->linecoding.parity = linecoding.parity;
return USB_OK;
}
/**
* @brief usb device class rx data process
* @param udev: to the structure of usbd_core_type
* @param recv_data: receive buffer
* @retval receive data len
*/
uint16_t usb_vcp_get_rxdata(void *udev, uint8_t *recv_data)
{
uint16_t i_index = 0;
uint16_t tmp_len = 0;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
if(pcdc->g_rx_completed == 0)
{
return 0;
}
pcdc->g_rx_completed = 0;
tmp_len = pcdc->g_rxlen;
for(i_index = 0; i_index < pcdc->g_rxlen; i_index ++)
{
recv_data[i_index] = pcdc->g_rx_buff[i_index];
}
usbd_ept_recv(pudev, USBD_CDC_BULK_OUT_EPT, pcdc->g_rx_buff, USBD_CDC_OUT_MAXPACKET_SIZE);
return tmp_len;
}
/**
* @brief usb device class send data
* @param udev: to the structure of usbd_core_type
* @param send_data: send data buffer
* @param len: send length
* @retval error status
*/
error_status usb_vcp_send_data(void *udev, uint8_t *send_data, uint16_t len)
{
error_status status = SUCCESS;
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
if(pcdc->g_tx_completed)
{
pcdc->g_tx_completed = 0;
usbd_ept_send(pudev, USBD_CDC_BULK_IN_EPT, send_data, len);
}
else
{
status = ERROR;
}
return status;
}
/**
* @brief usb device function
* @param udev: to the structure of usbd_core_type
* @param cmd: request number
* @param buff: request buffer
* @param len: buffer length
* @retval none
*/
static void usb_vcp_cmd_process(void *udev, uint8_t cmd, uint8_t *buff, uint16_t len)
{
UNUSED(len);
usbd_core_type *pudev = (usbd_core_type *)udev;
cdc_struct_type *pcdc = (cdc_struct_type *)pudev->class_handler->pdata;
switch(cmd)
{
case SET_LINE_CODING:
pcdc->linecoding.bitrate = (uint32_t)(buff[0] | (buff[1] << 8) | (buff[2] << 16) | (buff[3] <<24));
pcdc->linecoding.format = buff[4];
pcdc->linecoding.parity = buff[5];
pcdc->linecoding.data = buff[6];
#ifdef USB_VIRTUAL_COMPORT
/* set hardware usart */
usb_usart_config(pcdc->linecoding);
#endif
break;
case GET_LINE_CODING:
buff[0] = (uint8_t)pcdc->linecoding.bitrate;
buff[1] = (uint8_t)(pcdc->linecoding.bitrate >> 8);
buff[2] = (uint8_t)(pcdc->linecoding.bitrate >> 16);
buff[3] = (uint8_t)(pcdc->linecoding.bitrate >> 24);
buff[4] = (uint8_t)(pcdc->linecoding.format);
buff[5] = (uint8_t)(pcdc->linecoding.parity);
buff[6] = (uint8_t)(pcdc->linecoding.data);
break;
default:
break;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file cdc_class.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb cdc class file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __CDC_CLASS_H
#define __CDC_CLASS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "usb_std.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_cdc_class
* @{
*/
/** @defgroup USB_cdc_class_definition
* @{
*/
/**
* @brief usb cdc use endpoint define
*/
#define USBD_CDC_INT_EPT 0x82
#define USBD_CDC_BULK_IN_EPT 0x81
#define USBD_CDC_BULK_OUT_EPT 0x01
/**
* @brief usb cdc in and out max packet size define
*/
#define USBD_CDC_IN_MAXPACKET_SIZE 0x40
#define USBD_CDC_OUT_MAXPACKET_SIZE 0x40
#define USBD_CDC_CMD_MAXPACKET_SIZE 0x08
/**
* @}
*/
/** @defgroup USB_cdc_class_exported_types
* @{
*/
/**
* @brief usb cdc class struct
*/
typedef struct
{
uint32_t alt_setting;
uint8_t g_rx_buff[USBD_CDC_OUT_MAXPACKET_SIZE];
uint8_t g_cmd[USBD_CDC_CMD_MAXPACKET_SIZE];
uint8_t g_req;
uint16_t g_len, g_rxlen;
__IO uint8_t g_tx_completed, g_rx_completed;
linecoding_type linecoding;
}cdc_struct_type;
/**
* @}
*/
/** @defgroup USB_cdc_class_exported_functions
* @{
*/
extern usbd_class_handler cdc_class_handler;
uint16_t usb_vcp_get_rxdata(void *udev, uint8_t *recv_data);
error_status usb_vcp_send_data(void *udev, uint8_t *send_data, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file cdc_desc.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb cdc device descriptor
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "stdio.h"
#include "usb_std.h"
#include "usbd_sdr.h"
#include "usbd_core.h"
#include "cdc_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_cdc_desc
* @brief usb device cdc descriptor
* @{
*/
/** @defgroup USB_cdc_desc_private_functions
* @{
*/
static usbd_desc_t *get_device_descriptor(void);
static usbd_desc_t *get_device_qualifier(void);
static usbd_desc_t *get_device_configuration(void);
static usbd_desc_t *get_device_other_speed(void);
static usbd_desc_t *get_device_lang_id(void);
static usbd_desc_t *get_device_manufacturer_string(void);
static usbd_desc_t *get_device_product_string(void);
static usbd_desc_t *get_device_serial_string(void);
static usbd_desc_t *get_device_interface_string(void);
static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
/**
* @brief device descriptor handler structure
*/
usbd_desc_handler cdc_desc_handler =
{
get_device_descriptor,
get_device_qualifier,
get_device_configuration,
get_device_other_speed,
get_device_lang_id,
get_device_manufacturer_string,
get_device_product_string,
get_device_serial_string,
get_device_interface_string,
get_device_config_string,
};
/**
* @brief usb device standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
0x00, /* bcdUSB */
0x02,
0x02, /* bDeviceClass */
0x00, /* bDeviceSubClass */
0x00, /* bDeviceProtocol */
USB_MAX_EP0_SIZE, /* bMaxPacketSize */
LBYTE(USBD_CDC_VENDOR_ID), /* idVendor */
HBYTE(USBD_CDC_VENDOR_ID), /* idVendor */
LBYTE(USBD_CDC_PRODUCT_ID), /* idProduct */
HBYTE(USBD_CDC_PRODUCT_ID), /* idProduct */
0x00, /* bcdDevice rel. 2.00 */
0x02,
USB_MFC_STRING, /* Index of manufacturer string */
USB_PRODUCT_STRING, /* Index of product string */
USB_SERIAL_STRING, /* Index of serial number string */
1 /* bNumConfigurations */
};
/**
* @brief usb configuration standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_configuration[USBD_CDC_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
LBYTE(USBD_CDC_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
HBYTE(USBD_CDC_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
0x02, /* bNumInterfaces: 2 interface */
0x01, /* bConfigurationValue: configuration value */
0x00, /* iConfiguration: index of string descriptor describing
the configuration */
0xC0, /* bmAttributes: self powered */
0x32, /* MaxPower 100 mA: this current is used for detecting vbus */
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
0x00, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x01, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_CDC, /* bInterfaceClass: CDC class code */
0x02, /* bInterfaceSubClass: subclass code, Abstract Control Model*/
0x01, /* bInterfaceProtocol: protocol code, AT Command */
0x00, /* iInterface: index of string descriptor */
0x05, /* bFunctionLength: size of this descriptor in bytes */
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
USBD_CDC_SUBTYPE_HEADER, /* bDescriptorSubtype: Header function Descriptor 0x00*/
LBYTE(CDC_BCD_NUM),
HBYTE(CDC_BCD_NUM), /* bcdCDC: USB class definitions for communications */
0x05, /* bFunctionLength: size of this descriptor in bytes */
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
USBD_CDC_SUBTYPE_CMF, /* bDescriptorSubtype: Call Management function descriptor subtype 0x01 */
0x00, /* bmCapabilities: 0x00*/
0x01, /* bDataInterface: interface number of data class interface optionally used for call management */
0x04, /* bFunctionLength: size of this descriptor in bytes */
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
USBD_CDC_SUBTYPE_ACM, /* bDescriptorSubtype: Abstract Control Management functional descriptor subtype 0x02 */
0x02, /* bmCapabilities: Support Set_Line_Coding and Get_Line_Coding 0x02 */
0x05, /* bFunctionLength: size of this descriptor in bytes */
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
USBD_CDC_SUBTYPE_UFD, /* bDescriptorSubtype: Union Function Descriptor subtype 0x06 */
0x00, /* bControlInterface: The interface number of the communications or data class interface 0x00 */
0x01, /* bSubordinateInterface0: interface number of first subordinate interface in the union */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_CDC_INT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
LBYTE(USBD_CDC_CMD_MAXPACKET_SIZE),
HBYTE(USBD_CDC_CMD_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
CDC_HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
0x01, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x02, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_CDCDATA, /* bInterfaceClass: CDC-data class code */
0x00, /* bInterfaceSubClass: Data interface subclass code 0x00*/
0x00, /* bInterfaceProtocol: data class protocol code 0x00 */
0x00, /* iInterface: index of string descriptor */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_CDC_BULK_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
LBYTE(USBD_CDC_IN_MAXPACKET_SIZE),
HBYTE(USBD_CDC_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
0x00, /* bInterval: interval for polling endpoint for data transfers */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_CDC_BULK_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
LBYTE(USBD_CDC_OUT_MAXPACKET_SIZE),
HBYTE(USBD_CDC_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
0x00, /* bInterval: interval for polling endpoint for data transfers */
};
/**
* @brief usb string lang id
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_lang_id[USBD_CDC_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_CDC_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
0x09,
0x04,
};
/**
* @brief usb string serial
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_serial[USBD_CDC_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_CDC_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,
};
/* device descriptor */
static usbd_desc_t device_descriptor =
{
USB_DEVICE_DESC_LEN,
g_usbd_descriptor
};
/* config descriptor */
static usbd_desc_t config_descriptor =
{
USBD_CDC_CONFIG_DESC_SIZE,
g_usbd_configuration
};
/* langid descriptor */
static usbd_desc_t langid_descriptor =
{
USBD_CDC_SIZ_STRING_LANGID,
g_string_lang_id
};
/* serial descriptor */
static usbd_desc_t serial_descriptor =
{
USBD_CDC_SIZ_STRING_SERIAL,
g_string_serial
};
static usbd_desc_t vp_desc;
/**
* @brief standard usb unicode convert
* @param string: source string
* @param unicode_buf: unicode buffer
* @retval length
*/
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf)
{
uint16_t str_len = 0, id_pos = 2;
uint8_t *tmp_str = string;
while(*tmp_str != '\0')
{
str_len ++;
unicode_buf[id_pos ++] = *tmp_str ++;
unicode_buf[id_pos ++] = 0x00;
}
str_len = str_len * 2 + 2;
unicode_buf[0] = (uint8_t)str_len;
unicode_buf[1] = USB_DESCIPTOR_TYPE_STRING;
return str_len;
}
/**
* @brief usb int convert to unicode
* @param value: int value
* @param pbus: unicode buffer
* @param len: length
* @retval none
*/
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len)
{
uint8_t idx = 0;
for( idx = 0 ; idx < len ; idx ++)
{
if( ((value >> 28)) < 0xA )
{
pbuf[ 2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/**
* @brief usb get serial number
* @param none
* @retval none
*/
static void get_serial_num(void)
{
uint32_t serial0, serial1, serial2;
serial0 = *(uint32_t*)MCU_ID1;
serial1 = *(uint32_t*)MCU_ID2;
serial2 = *(uint32_t*)MCU_ID3;
serial0 += serial2;
if (serial0 != 0)
{
usbd_int_to_unicode (serial0, &g_string_serial[2] ,8);
usbd_int_to_unicode (serial1, &g_string_serial[18] ,4);
}
}
/**
* @brief get device descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_descriptor(void)
{
return &device_descriptor;
}
/**
* @brief get device qualifier
* @param none
* @retval usbd_desc
*/
static usbd_desc_t * get_device_qualifier(void)
{
return NULL;
}
/**
* @brief get config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_configuration(void)
{
return &config_descriptor;
}
/**
* @brief get other speed descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_other_speed(void)
{
return NULL;
}
/**
* @brief get lang id descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_lang_id(void)
{
return &langid_descriptor;
}
/**
* @brief get manufacturer descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_manufacturer_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_CDC_DESC_MANUFACTURER_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get product descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_product_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_CDC_DESC_PRODUCT_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get serial descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_serial_string(void)
{
get_serial_num();
return &serial_descriptor;
}
/**
* @brief get interface descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_interface_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_CDC_DESC_INTERFACE_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get device config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_config_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_CDC_DESC_CONFIGURATION_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file cdc_desc.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb cdc descriptor header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __CDC_DESC_H
#define __CDC_DESC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cdc_class.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_cdc_desc
* @{
*/
/** @defgroup USB_cdc_desc_definition
* @{
*/
/**
* @brief usb bcd number define
*/
#define CDC_BCD_NUM 0x0110
/**
* @brief usb vendor id and product id define
*/
#define USBD_CDC_VENDOR_ID 0x2E3C
#define USBD_CDC_PRODUCT_ID 0x5740
/**
* @brief usb descriptor size define
*/
#define USBD_CDC_CONFIG_DESC_SIZE 67
#define USBD_CDC_SIZ_STRING_LANGID 4
#define USBD_CDC_SIZ_STRING_SERIAL 0x1A
/**
* @brief usb string define(vendor, product configuration, interface)
*/
#define USBD_CDC_DESC_MANUFACTURER_STRING "Artery"
#define USBD_CDC_DESC_PRODUCT_STRING "AT32 Virtual Com Port "
#define USBD_CDC_DESC_CONFIGURATION_STRING "Virtual ComPort Config"
#define USBD_CDC_DESC_INTERFACE_STRING "Virtual ComPort Interface"
/**
* @brief usb endpoint interval define
*/
#define CDC_HID_BINTERVAL_TIME 0xFF
/**
* @brief usb mcu id address deine
*/
#define MCU_ID1 (0x1FFFF7E8)
#define MCU_ID2 (0x1FFFF7EC)
#define MCU_ID3 (0x1FFFF7F0)
/**
* @}
*/
extern usbd_desc_handler cdc_desc_handler;
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file hid_iap_class.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb hid iap class type
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usbd_core.h"
#include "hid_iap_class.h"
#include "hid_iap_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_hid_iap_class
* @brief usb device class hid iap demo
* @{
*/
/** @defgroup USB_hid_iap_class_private_functions
* @{
*/
static usb_sts_type class_init_handler(void *udev);
static usb_sts_type class_clear_handler(void *udev);
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup);
static usb_sts_type class_ept0_tx_handler(void *udev);
static usb_sts_type class_ept0_rx_handler(void *udev);
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_sof_handler(void *udev);
static usb_sts_type class_event_handler(void *udev, usbd_event_type event);
iap_info_type iap_info;
/* usb device class handler */
usbd_class_handler hid_iap_class_handler =
{
class_init_handler,
class_clear_handler,
class_setup_handler,
class_ept0_tx_handler,
class_ept0_rx_handler,
class_in_handler,
class_out_handler,
class_sof_handler,
class_event_handler,
&iap_info
};
/**
* @brief initialize usb custom hid endpoint
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_init_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
iap_info_type *piap = (iap_info_type *)pudev->class_handler->pdata;
/* open hid iap in endpoint */
usbd_ept_open(pudev, USBD_HIDIAP_IN_EPT, EPT_INT_TYPE, USBD_HIDIAP_IN_MAXPACKET_SIZE);
/* open hid iap out endpoint */
usbd_ept_open(pudev, USBD_HIDIAP_OUT_EPT, EPT_INT_TYPE, USBD_HIDIAP_OUT_MAXPACKET_SIZE);
/* set out endpoint to receive status */
usbd_ept_recv(pudev, USBD_HIDIAP_OUT_EPT, piap->g_rxhid_buff, USBD_HIDIAP_OUT_MAXPACKET_SIZE);
return status;
}
/**
* @brief clear endpoint or other state
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_clear_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* close hid iap in endpoint */
usbd_ept_close(pudev, USBD_HIDIAP_IN_EPT);
/* close hid iap out endpoint */
usbd_ept_close(pudev, USBD_HIDIAP_OUT_EPT);
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: to the structure of usbd_core_type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
iap_info_type *piap = (iap_info_type *)pudev->class_handler->pdata;
uint16_t len;
uint8_t *buf;
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
{
/* class request */
case USB_REQ_TYPE_CLASS:
switch(setup->bRequest)
{
case HID_REQ_SET_PROTOCOL:
piap->hid_protocol = (uint8_t)setup->wValue;
break;
case HID_REQ_GET_PROTOCOL:
usbd_ctrl_send(pudev, (uint8_t *)&piap->hid_protocol, 1);
break;
case HID_REQ_SET_IDLE:
piap->hid_set_idle = (uint8_t)(setup->wValue >> 8);
break;
case HID_REQ_GET_IDLE:
usbd_ctrl_send(pudev, (uint8_t *)&piap->hid_set_idle, 1);
break;
case HID_REQ_SET_REPORT:
piap->hid_state = HID_REQ_SET_REPORT;
usbd_ctrl_recv(pudev, piap->hid_set_report, setup->wLength);
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
/* standard request */
case USB_REQ_TYPE_STANDARD:
switch(setup->bRequest)
{
case USB_STD_REQ_GET_DESCRIPTOR:
if(setup->wValue >> 8 == HID_REPORT_DESC)
{
len = MIN(USBD_HIDIAP_SIZ_REPORT_DESC, setup->wLength);
buf = (uint8_t *)g_usbd_hidiap_report;
}
else if(setup->wValue >> 8 == HID_DESCRIPTOR_TYPE)
{
len = MIN(9, setup->wLength);
buf = (uint8_t *)g_hidiap_usb_desc;
}
usbd_ctrl_send(pudev, (uint8_t *)buf, len);
break;
case USB_STD_REQ_GET_INTERFACE:
usbd_ctrl_send(pudev, (uint8_t *)&piap->alt_setting, 1);
break;
case USB_STD_REQ_SET_INTERFACE:
piap->alt_setting = setup->wValue;
break;
default:
break;
}
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
return status;
}
/**
* @brief usb device endpoint 0 in status stage complete
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_tx_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
return status;
}
/**
* @brief usb device endpoint 0 out status stage complete
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_rx_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
iap_info_type *piap = (iap_info_type *)pudev->class_handler->pdata;
uint32_t recv_len = usbd_get_recv_len(pudev, 0);
/* ...user code... */
if( piap->hid_state == HID_REQ_SET_REPORT)
{
/* hid buffer process */
piap->hid_state = 0;
}
return status;
}
/**
* @brief usb device transmision complete handler
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
/* ...user code...
trans next packet data
*/
usbd_hid_iap_in_complete(udev);
return status;
}
/**
* @brief usb device endpoint receive data
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
iap_info_type *piap = (iap_info_type *)pudev->class_handler->pdata;
/* get endpoint receive data length */
uint32_t recv_len = usbd_get_recv_len(pudev, ept_num);
/* hid iap process */
usbd_hid_iap_process(udev, piap->g_rxhid_buff, recv_len);
/* start receive next packet */
usbd_ept_recv(pudev, USBD_HIDIAP_OUT_EPT, piap->g_rxhid_buff, USBD_HIDIAP_OUT_MAXPACKET_SIZE);
return status;
}
/**
* @brief usb device sof handler
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_sof_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
return status;
}
/**
* @brief usb device event handler
* @param udev: to the structure of usbd_core_type
* @param event: usb device event
* @retval status of usb_sts_type
*/
static usb_sts_type class_event_handler(void *udev, usbd_event_type event)
{
usb_sts_type status = USB_OK;
switch(event)
{
case USBD_RESET_EVENT:
/* ...user code... */
break;
case USBD_SUSPEND_EVENT:
/* ...user code... */
break;
case USBD_WAKEUP_EVENT:
/* ...user code... */
break;
default:
break;
}
return status;
}
/**
* @brief usb device class send report
* @param udev: to the structure of usbd_core_type
* @param report: report buffer
* @param len: report length
* @retval status of usb_sts_type
*/
usb_sts_type usb_iap_class_send_report(void *udev, uint8_t *report, uint16_t len)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
if(usbd_connect_state_get(pudev) == USB_CONN_STATE_CONFIGURED)
usbd_ept_send(pudev, USBD_HIDIAP_IN_EPT, report, len);
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file hid_iap_class.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb hid iap header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __HID_IAP_CLASS_H
#define __HID_IAP_CLASS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "usb_std.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_hid_iap_class
* @{
*/
/** @defgroup USB_hid_iap_class_definition
* @{
*/
#define USBD_HIDIAP_IN_EPT 0x81
#define USBD_HIDIAP_OUT_EPT 0x01
#define USBD_HIDIAP_IN_MAXPACKET_SIZE 0x40
#define USBD_HIDIAP_OUT_MAXPACKET_SIZE 0x40
#define FLASH_SIZE_REG() ((*(uint32_t *)0x1FFFF7E0) & 0xFFFF) /*Get Flash size*/
#define KB_TO_B(kb) ((kb) << 10)
#define SECTOR_SIZE_1K 0x400
#define SECTOR_SIZE_2K 0x800
#define SECTOR_SIZE_4K 0x1000
/**
* @brief iap command
*/
#define IAP_CMD_IDLE 0x5AA0
#define IAP_CMD_START 0x5AA1
#define IAP_CMD_ADDR 0x5AA2
#define IAP_CMD_DATA 0x5AA3
#define IAP_CMD_FINISH 0x5AA4
#define IAP_CMD_CRC 0x5AA5
#define IAP_CMD_JMP 0x5AA6
#define IAP_CMD_GET 0x5AA7
#define HID_IAP_BUFFER_LEN 1024
#define IAP_UPGRADE_COMPLETE_FLAG 0x41544B38
#define CONVERT_ENDIAN(dwValue) ((dwValue >> 24) | ((dwValue >> 8) & 0xFF00) | \
((dwValue << 8) & 0xFF0000) | (dwValue << 24) )
#define IAP_ACK 0xFF00
#define IAP_NACK 0x00FF
typedef enum
{
IAP_SUCCESS,
IAP_WAIT,
IAP_FAILED
}iap_result_type;
typedef enum
{
IAP_STS_IDLE,
IAP_STS_START,
IAP_STS_ADDR,
IAP_STS_DATA,
IAP_STS_FINISH,
IAP_STS_CRC,
IAP_STS_JMP_WAIT,
IAP_STS_JMP,
}iap_machine_state_type;
typedef struct
{
uint8_t iap_fifo[HID_IAP_BUFFER_LEN];
uint8_t iap_rx[USBD_HIDIAP_OUT_MAXPACKET_SIZE];
uint8_t iap_tx[USBD_HIDIAP_IN_MAXPACKET_SIZE];
uint32_t fifo_length;
uint32_t tx_length;
uint32_t app_address;
uint32_t iap_address;
uint32_t flag_address;
uint32_t flash_start_address;
uint32_t flash_end_address;
uint32_t sector_size;
uint32_t flash_size;
uint32_t respond_flag;
uint8_t g_rxhid_buff[USBD_HIDIAP_OUT_MAXPACKET_SIZE];
uint32_t hid_protocol;
uint32_t hid_set_idle;
uint32_t alt_setting;
uint32_t hid_state;
uint8_t hid_set_report[64];
iap_machine_state_type state;
}iap_info_type;
extern usbd_class_handler hid_iap_class_handler;
extern iap_info_type iap_info;
usb_sts_type usb_iap_class_send_report(void *udev, uint8_t *report, uint16_t len);
iap_result_type usbd_hid_iap_process(void *udev, uint8_t *report, uint16_t len);
void usbd_hid_iap_in_complete(void *udev);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file hid_iap_desc.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb hid iap device descriptor
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usb_std.h"
#include "usbd_sdr.h"
#include "usbd_core.h"
#include "hid_iap_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_hid_iap_desc
* @brief usb device hid_iap descriptor
* @{
*/
/** @defgroup USB_hid_iap_desc_private_functions
* @{
*/
static usbd_desc_t *get_device_descriptor(void);
static usbd_desc_t *get_device_qualifier(void);
static usbd_desc_t *get_device_configuration(void);
static usbd_desc_t *get_device_other_speed(void);
static usbd_desc_t *get_device_lang_id(void);
static usbd_desc_t *get_device_manufacturer_string(void);
static usbd_desc_t *get_device_product_string(void);
static usbd_desc_t *get_device_serial_string(void);
static usbd_desc_t *get_device_interface_string(void);
static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
/**
* @brief hid device descriptor handler structure
*/
usbd_desc_handler hid_iap_desc_handler =
{
get_device_descriptor,
get_device_qualifier,
get_device_configuration,
get_device_other_speed,
get_device_lang_id,
get_device_manufacturer_string,
get_device_product_string,
get_device_serial_string,
get_device_interface_string,
get_device_config_string,
};
/**
* @brief usb device standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
0x00, /* bcdUSB */
0x02,
0x00, /* bDeviceClass */
0x00, /* bDeviceSubClass */
0x00, /* bDeviceProtocol */
USB_MAX_EP0_SIZE, /* bMaxPacketSize */
LBYTE(USBD_HIDIAP_VENDOR_ID), /* idVendor */
HBYTE(USBD_HIDIAP_VENDOR_ID), /* idVendor */
LBYTE(USBD_HIDIAP_PRODUCT_ID), /* idProduct */
HBYTE(USBD_HIDIAP_PRODUCT_ID), /* idProduct */
0x00, /* bcdDevice rel. 2.00 */
0x02,
USB_MFC_STRING, /* Index of manufacturer string */
USB_PRODUCT_STRING, /* Index of product string */
USB_SERIAL_STRING, /* Index of serial number string */
1 /* bNumConfigurations */
};
/**
* @brief usb configuration standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_configuration[USBD_HIDIAP_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
LBYTE(USBD_HIDIAP_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
HBYTE(USBD_HIDIAP_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
0x01, /* bNumInterfaces: 1 interface */
0x01, /* bConfigurationValue: configuration value */
0x00, /* iConfiguration: index of string descriptor describing
the configuration */
0xC0, /* bmAttributes: self powered */
0x32, /* MaxPower 100 mA: this current is used for detecting vbus */
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
0x00, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x02, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_HID, /* bInterfaceClass: class code hid */
0x00, /* bInterfaceSubClass: subclass code */
0x00, /* bInterfaceProtocol: protocol code */
0x00, /* iInterface: index of string descriptor */
0x09, /* bLength: size of HID descriptor in bytes */
HID_CLASS_DESC_HID, /* bDescriptorType: HID descriptor type */
LBYTE(HIDIAP_BCD_NUM),
HBYTE(HIDIAP_BCD_NUM), /* bcdHID: HID class specification release number */
0x00, /* bCountryCode: hardware target conutry */
0x01, /* bNumDescriptors: number of HID class descriptor to follow */
HID_CLASS_DESC_REPORT, /* bDescriptorType: report descriptor type */
LBYTE(sizeof(g_usbd_hidiap_report)),
HBYTE(sizeof(g_usbd_hidiap_report)), /* wDescriptorLength: total length of reprot descriptor */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_HIDIAP_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
LBYTE(USBD_HIDIAP_IN_MAXPACKET_SIZE),
HBYTE(USBD_HIDIAP_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HIDIAP_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_HIDIAP_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
LBYTE(USBD_HIDIAP_OUT_MAXPACKET_SIZE),
HBYTE(USBD_HIDIAP_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HIDIAP_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
};
/**
* @brief usb hid report descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_hidiap_report[USBD_HIDIAP_SIZ_REPORT_DESC] ALIGNED_TAIL =
{
0x06, 0xFF, 0x00, /* USAGE_PAGE(Vendor Page:0xFF00) */
0x09, 0x01, /* USAGE (Demo Kit) */
0xa1, 0x01, /* COLLECTION (Application) */
/* 6 */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0xFF, /* LOGICAL_MAXIMUM (255) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x40, /* REPORT_COUNT (64) */
0x09, 0x01,
0x81, 0x02,
0x95, 0x40,
0x09, 0x01,
0x91, 0x02,
0x95, 0x01,
0x09, 0x01,
0xB1, 0x02,
0xC0
};
/**
* @brief usb hid descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_hidiap_usb_desc[9] ALIGNED_TAIL =
{
0x09, /* bLength: size of HID descriptor in bytes */
HID_CLASS_DESC_HID, /* bDescriptorType: HID descriptor type */
LBYTE(HIDIAP_BCD_NUM),
HBYTE(HIDIAP_BCD_NUM), /* bcdHID: HID class specification release number */
0x00, /* bCountryCode: hardware target conutry */
0x01, /* bNumDescriptors: number of HID class descriptor to follow */
HID_CLASS_DESC_REPORT, /* bDescriptorType: report descriptor type */
LBYTE(sizeof(g_usbd_hidiap_report)),
HBYTE(sizeof(g_usbd_hidiap_report)), /* wDescriptorLength: total length of reprot descriptor */
};
/**
* @brief usb string lang id
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_lang_id[USBD_HIDIAP_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_HIDIAP_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
0x09,
0x04,
};
/**
* @brief usb string serial
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_serial[USBD_HIDIAP_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_HIDIAP_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,
};
/* device descriptor */
static usbd_desc_t device_descriptor =
{
USB_DEVICE_DESC_LEN,
g_usbd_descriptor
};
/* config descriptor */
static usbd_desc_t config_descriptor =
{
USBD_HIDIAP_CONFIG_DESC_SIZE,
g_usbd_configuration
};
/* langid descriptor */
static usbd_desc_t langid_descriptor =
{
USBD_HIDIAP_SIZ_STRING_LANGID,
g_string_lang_id
};
/* serial descriptor */
static usbd_desc_t serial_descriptor =
{
USBD_HIDIAP_SIZ_STRING_SERIAL,
g_string_serial
};
static usbd_desc_t vp_desc;
/**
* @brief standard usb unicode convert
* @param string: source string
* @param unicode_buf: unicode buffer
* @retval length
*/
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf)
{
uint16_t str_len = 0, id_pos = 2;
uint8_t *tmp_str = string;
while(*tmp_str != '\0')
{
str_len ++;
unicode_buf[id_pos ++] = *tmp_str ++;
unicode_buf[id_pos ++] = 0x00;
}
str_len = str_len * 2 + 2;
unicode_buf[0] = str_len;
unicode_buf[1] = USB_DESCIPTOR_TYPE_STRING;
return str_len;
}
/**
* @brief usb int convert to unicode
* @param value: int value
* @param pbus: unicode buffer
* @param len: length
* @retval none
*/
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len)
{
uint8_t idx = 0;
for( idx = 0 ; idx < len ; idx ++)
{
if( ((value >> 28)) < 0xA )
{
pbuf[ 2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/**
* @brief usb get serial number
* @param none
* @retval none
*/
static void get_serial_num(void)
{
uint32_t serial0, serial1, serial2;
serial0 = *(uint32_t*)MCU_ID1;
serial1 = *(uint32_t*)MCU_ID2;
serial2 = *(uint32_t*)MCU_ID3;
serial0 += serial2;
if (serial0 != 0)
{
usbd_int_to_unicode (serial0, &g_string_serial[2] ,8);
usbd_int_to_unicode (serial1, &g_string_serial[18] ,4);
}
}
/**
* @brief get device descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_descriptor(void)
{
return &device_descriptor;
}
/**
* @brief get device qualifier
* @param none
* @retval usbd_desc
*/
static usbd_desc_t * get_device_qualifier(void)
{
return NULL;
}
/**
* @brief get config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_configuration(void)
{
return &config_descriptor;
}
/**
* @brief get other speed descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_other_speed(void)
{
return NULL;
}
/**
* @brief get lang id descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_lang_id(void)
{
return &langid_descriptor;
}
/**
* @brief get manufacturer descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_manufacturer_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_HIDIAP_DESC_MANUFACTURER_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get product descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_product_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_HIDIAP_DESC_PRODUCT_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get serial descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_serial_string(void)
{
get_serial_num();
return &serial_descriptor;
}
/**
* @brief get interface descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_interface_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_HIDIAP_DESC_INTERFACE_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get device config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_config_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_HIDIAP_DESC_CONFIGURATION_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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lib/main/AT32F43x/Middlewares/AT/AT32_USB_Device_Library/Class/usbd_class/hid_iap/hid_iap_desc.h Normal file
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/**
**************************************************************************
* @file hid_iap_desc.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb hid iap descriptor header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __HID_IAP_DESC_H
#define __HID_IAP_DESC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "hid_iap_class.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_hid_iap_desc
* @{
*/
/** @defgroup USB_hid_iap_desc_definition
* @{
*/
#define HIDIAP_BCD_NUM 0x0110
#define USBD_HIDIAP_VENDOR_ID 0x2E3C
#define USBD_HIDIAP_PRODUCT_ID 0xAF01
#define USBD_HIDIAP_CONFIG_DESC_SIZE 41
#define USBD_HIDIAP_SIZ_REPORT_DESC 32
#define USBD_HIDIAP_SIZ_STRING_LANGID 4
#define USBD_HIDIAP_SIZ_STRING_SERIAL 0x1A
#define USBD_HIDIAP_DESC_MANUFACTURER_STRING "Artery"
#define USBD_HIDIAP_DESC_PRODUCT_STRING "HID IAP"
#define USBD_HIDIAP_DESC_CONFIGURATION_STRING "HID IAP Config"
#define USBD_HIDIAP_DESC_INTERFACE_STRING "HID IAP Interface"
#define HIDIAP_BINTERVAL_TIME 0x01
#define MCU_ID1 (0x1FFFF7E8)
#define MCU_ID2 (0x1FFFF7EC)
#define MCU_ID3 (0x1FFFF7F0)
extern uint8_t g_usbd_hidiap_report[USBD_HIDIAP_SIZ_REPORT_DESC];
extern uint8_t g_hidiap_usb_desc[9];
extern usbd_desc_handler hid_iap_desc_handler;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file msc_bot_scsi.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb mass storage bulk-only transport and scsi command
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "msc_bot_scsi.h"
#include "msc/at32_msc_diskio.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_msc_bot_scsi
* @brief usb device class mass storage demo
* @{
*/
/** @defgroup USB_msc_bot_functions
* @{
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t page00_inquiry_data[] ALIGNED_TAIL = {
0x00,
0x00,
0x00,
0x00,
0x00,
};
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD sense_type sense_data ALIGNED_TAIL =
{
0x70,
0x00,
SENSE_KEY_ILLEGAL_REQUEST,
0x00000000,
0x0A,
0x00000000,
0x20,
0x00,
0x00000000
};
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t mode_sense6_data[8] ALIGNED_TAIL =
{
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t mode_sense10_data[8] ALIGNED_TAIL =
{
0x00,
0x06,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
/**
* @brief initialize bulk-only transport and scsi
* @param udev: to the structure of usbd_core_type
* @retval none
*/
void bot_scsi_init(void *udev)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->msc_state = MSC_STATE_MACHINE_IDLE;
pmsc->bot_status = MSC_BOT_STATE_IDLE;
pmsc->max_lun = MSC_SUPPORT_MAX_LUN - 1;
pmsc->csw_struct.dCSWSignature = CSW_DCSWSIGNATURE;
pmsc->csw_struct.dCSWDataResidue = 0;
pmsc->csw_struct.dCSWSignature = 0;
pmsc->csw_struct.dCSWTag = CSW_BCSWSTATUS_PASS;
usbd_flush_tx_fifo(pudev, USBD_MSC_BULK_IN_EPT&0x7F);
/* set out endpoint to receive status */
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT, (uint8_t *)&pmsc->cbw_struct, CBW_CMD_LENGTH);
}
/**
* @brief reset bulk-only transport and scsi
* @param udev: to the structure of usbd_core_type
* @retval none
*/
void bot_scsi_reset(void *udev)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->msc_state = MSC_STATE_MACHINE_IDLE;
pmsc->bot_status = MSC_BOT_STATE_RECOVERY;
pmsc->max_lun = MSC_SUPPORT_MAX_LUN - 1;
usbd_flush_tx_fifo(pudev, USBD_MSC_BULK_IN_EPT&0x7F);
/* set out endpoint to receive status */
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT, (uint8_t *)&pmsc->cbw_struct, CBW_CMD_LENGTH);
}
/**
* @brief bulk-only transport data in handler
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval none
*/
void bot_scsi_datain_handler(void *udev, uint8_t ept_num)
{
UNUSED(ept_num);
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
switch(pmsc->msc_state)
{
case MSC_STATE_MACHINE_DATA_IN:
if(bot_scsi_cmd_process(udev) != USB_OK)
{
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_FAILED);
}
break;
case MSC_STATE_MACHINE_LAST_DATA:
case MSC_STATE_MACHINE_SEND_DATA:
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_PASS);
break;
default:
break;
}
}
/**
* @brief bulk-only transport data out handler
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval none
*/
void bot_scsi_dataout_handler(void *udev, uint8_t ept_num)
{
UNUSED(ept_num);
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
switch(pmsc->msc_state)
{
case MSC_STATE_MACHINE_IDLE:
bot_cbw_decode(udev);
break;
case MSC_STATE_MACHINE_DATA_OUT:
if(bot_scsi_cmd_process(udev) != USB_OK)
{
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_FAILED);
}
break;
}
}
/**
* @brief bulk-only cbw decode
* @param udev: to the structure of usbd_core_type
* @retval none
*/
void bot_cbw_decode(void *udev)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->csw_struct.dCSWTag = pmsc->cbw_struct.dCBWTage;
pmsc->csw_struct.dCSWDataResidue = pmsc->cbw_struct.dCBWDataTransferLength;
/* check param */
if((pmsc->cbw_struct.dCBWSignature != CBW_DCBWSIGNATURE) ||
(usbd_get_recv_len(pudev, USBD_MSC_BULK_OUT_EPT) != CBW_CMD_LENGTH)
|| (pmsc->cbw_struct.bCBWLUN > MSC_SUPPORT_MAX_LUN) ||
(pmsc->cbw_struct.bCBWCBLength < 1) || (pmsc->cbw_struct.bCBWCBLength > 16))
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
pmsc->bot_status = MSC_BOT_STATE_ERROR;
bot_scsi_stall(udev);
}
else
{
if(bot_scsi_cmd_process(udev) != USB_OK)
{
bot_scsi_stall(udev);
}
else if((pmsc->msc_state != MSC_STATE_MACHINE_DATA_IN) &&
(pmsc->msc_state != MSC_STATE_MACHINE_DATA_OUT) &&
(pmsc->msc_state != MSC_STATE_MACHINE_LAST_DATA))
{
if(pmsc->data_len == 0)
{
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_PASS);
}
else if(pmsc->data_len > 0)
{
bot_scsi_send_data(udev, pmsc->data, pmsc->data_len);
}
}
}
}
/**
* @brief send bot data
* @param udev: to the structure of usbd_core_type
* @param buffer: data buffer
* @param len: data len
* @retval none
*/
void bot_scsi_send_data(void *udev, uint8_t *buffer, uint32_t len)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint32_t data_len = MIN(len, pmsc->cbw_struct.dCBWDataTransferLength);
pmsc->csw_struct.dCSWDataResidue -= data_len;
pmsc->csw_struct.bCSWStatus = CSW_BCSWSTATUS_PASS;
pmsc->msc_state = MSC_STATE_MACHINE_SEND_DATA;
usbd_ept_send(pudev, USBD_MSC_BULK_IN_EPT,
buffer, data_len);
}
/**
* @brief send command status
* @param udev: to the structure of usbd_core_type
* @param status: csw status
* @retval none
*/
void bot_scsi_send_csw(void *udev, uint8_t status)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->csw_struct.bCSWStatus = status;
pmsc->csw_struct.dCSWSignature = CSW_DCSWSIGNATURE;
pmsc->msc_state = MSC_STATE_MACHINE_IDLE;
usbd_ept_send(pudev, USBD_MSC_BULK_IN_EPT,
(uint8_t *)&pmsc->csw_struct, CSW_CMD_LENGTH);
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT,
(uint8_t *)&pmsc->cbw_struct, CBW_CMD_LENGTH);
}
/**
* @brief send scsi sense code
* @param udev: to the structure of usbd_core_type
* @param sense_key: sense key
* @param asc: asc
* @retval none
*/
void bot_scsi_sense_code(void *udev, uint8_t sense_key, uint8_t asc)
{
UNUSED(udev);
sense_data.sense_key = sense_key;
sense_data.asc = asc;
}
/**
* @brief check address
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @param blk_offset: blk offset address
* @param blk_count: blk number
* @retval usb_sts_type
*/
usb_sts_type bot_scsi_check_address(void *udev, uint8_t lun, uint32_t blk_offset, uint32_t blk_count)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
if((blk_offset + blk_count) > pmsc->blk_nbr[lun])
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
return USB_FAIL;
}
return USB_OK;
}
/**
* @brief bot endpoint stall
* @param udev: to the structure of usbd_core_type
* @retval none
*/
void bot_scsi_stall(void *udev)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
if((pmsc->cbw_struct.dCBWDataTransferLength != 0) &&
(pmsc->cbw_struct.bmCBWFlags == 0) &&
pmsc->bot_status == MSC_BOT_STATE_IDLE)
{
usbd_set_stall(pudev, USBD_MSC_BULK_OUT_EPT);
}
usbd_set_stall(pudev, USBD_MSC_BULK_IN_EPT);
if(pmsc->bot_status == MSC_BOT_STATE_ERROR)
{
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT,
(uint8_t *)&pmsc->cbw_struct, CBW_CMD_LENGTH);
}
}
/**
* @brief bulk-only transport scsi command test unit
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_test_unit(void *udev, uint8_t lun)
{
UNUSED(lun);
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
if(pmsc->cbw_struct.dCBWDataTransferLength != 0)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
return USB_FAIL;
}
pmsc->data_len = 0;
return status;
}
/**
* @brief bulk-only transport scsi command inquiry
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_inquiry(void *udev, uint8_t lun)
{
uint8_t *pdata;
uint32_t trans_len = 0;
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
if(pmsc->cbw_struct.CBWCB[1] & 0x01)
{
pdata = page00_inquiry_data;
trans_len = 5;
}
else
{
pdata = get_inquiry(lun);
if(pmsc->cbw_struct.dCBWDataTransferLength < SCSI_INQUIRY_DATA_LENGTH)
{
trans_len = pmsc->cbw_struct.dCBWDataTransferLength;
}
else
{
trans_len = SCSI_INQUIRY_DATA_LENGTH;
}
}
pmsc->data_len = trans_len;
while(trans_len)
{
trans_len --;
pmsc->data[trans_len] = pdata[trans_len];
}
return status;
}
/**
* @brief bulk-only transport scsi command start stop
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_start_stop(void *udev, uint8_t lun)
{
UNUSED(lun);
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->data_len = 0;
return USB_OK;
}
/**
* @brief bulk-only transport scsi command meidum removal
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_allow_medium_removal(void *udev, uint8_t lun)
{
UNUSED(lun);
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->data_len = 0;
return USB_OK;
}
/**
* @brief bulk-only transport scsi command mode sense6
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_mode_sense6(void *udev, uint8_t lun)
{
UNUSED(lun);
uint8_t data_len = 8;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->data_len = 8;
while(data_len)
{
data_len --;
pmsc->data[data_len] = mode_sense6_data[data_len];
};
return USB_OK;
}
/**
* @brief bulk-only transport scsi command mode sense10
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_mode_sense10(void *udev, uint8_t lun)
{
UNUSED(lun);
uint8_t data_len = 8;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
pmsc->data_len = 8;
while(data_len)
{
data_len --;
pmsc->data[data_len] = mode_sense10_data[data_len];
};
return USB_OK;
}
/**
* @brief bulk-only transport scsi command capacity
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_capacity(void *udev, uint8_t lun)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *pdata = pmsc->data;
msc_disk_capacity(lun, &pmsc->blk_nbr[lun], &pmsc->blk_size[lun]);
pdata[0] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 24);
pdata[1] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 16);
pdata[2] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 8);
pdata[3] = (uint8_t)((pmsc->blk_nbr[lun] - 1));
pdata[4] = (uint8_t)((pmsc->blk_size[lun]) >> 24);
pdata[5] = (uint8_t)((pmsc->blk_size[lun]) >> 16);
pdata[6] = (uint8_t)((pmsc->blk_size[lun]) >> 8);
pdata[7] = (uint8_t)((pmsc->blk_size[lun]));
pmsc->data_len = 8;
return USB_OK;
}
/**
* @brief bulk-only transport scsi command format capacity
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_format_capacity(void *udev, uint8_t lun)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *pdata = pmsc->data;
pdata[0] = 0;
pdata[1] = 0;
pdata[2] = 0;
pdata[3] = 0x08;
msc_disk_capacity(lun, &pmsc->blk_nbr[lun], &pmsc->blk_size[lun]);
pdata[4] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 24);
pdata[5] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 16);
pdata[6] = (uint8_t)((pmsc->blk_nbr[lun] - 1) >> 8);
pdata[7] = (uint8_t)((pmsc->blk_nbr[lun] - 1));
pdata[8] = 0x02;
pdata[9] = (uint8_t)((pmsc->blk_size[lun]) >> 16);
pdata[10] = (uint8_t)((pmsc->blk_size[lun]) >> 8);
pdata[11] = (uint8_t)((pmsc->blk_size[lun]));
pmsc->data_len = 12;
return USB_OK;
}
/**
* @brief bulk-only transport scsi command request sense
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_request_sense(void *udev, uint8_t lun)
{
UNUSED(lun);
uint32_t trans_len = 0x12;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *pdata = pmsc->data;
uint8_t *sdata = (uint8_t *)&sense_data;
while(trans_len)
{
trans_len --;
pdata[trans_len] = sdata[trans_len];
}
if(pmsc->cbw_struct.dCBWDataTransferLength < REQ_SENSE_STANDARD_DATA_LEN)
{
pmsc->data_len = pmsc->cbw_struct.dCBWDataTransferLength;
}
else
{
pmsc->data_len = REQ_SENSE_STANDARD_DATA_LEN;
}
return USB_OK;
}
/**
* @brief bulk-only transport scsi command verify
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_verify(void *udev, uint8_t lun)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *cmd = pmsc->cbw_struct.CBWCB;
if((pmsc->cbw_struct.CBWCB[1] & 0x02) == 0x02)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
return USB_FAIL;
}
pmsc->blk_addr = cmd[2] << 24 | cmd[3] << 16 | cmd[4] << 8 | cmd[5];
pmsc->blk_len = cmd[7] << 8 | cmd[8];
if(bot_scsi_check_address(udev, lun, pmsc->blk_addr, pmsc->blk_len) != USB_OK)
{
return USB_FAIL;
}
pmsc->data_len = 0;
return USB_OK;
}
/**
* @brief bulk-only transport scsi command read10
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_read10(void *udev, uint8_t lun)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *cmd = pmsc->cbw_struct.CBWCB;
uint32_t len;
if(pmsc->msc_state == MSC_STATE_MACHINE_IDLE)
{
if((pmsc->cbw_struct.bmCBWFlags & 0x80) != 0x80)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
return USB_FAIL;
}
pmsc->blk_addr = cmd[2] << 24 | cmd[3] << 16 | cmd[4] << 8 | cmd[5];
pmsc->blk_len = cmd[7] << 8 | cmd[8];
if(bot_scsi_check_address(udev, lun, pmsc->blk_addr, pmsc->blk_len) != USB_OK)
{
return USB_FAIL;
}
pmsc->blk_addr *= pmsc->blk_size[lun];
pmsc->blk_len *= pmsc->blk_size[lun];
if(pmsc->cbw_struct.dCBWDataTransferLength != pmsc->blk_len)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
return USB_FAIL;
}
pmsc->msc_state = MSC_STATE_MACHINE_DATA_IN;
}
pmsc->data_len = MSC_MAX_DATA_BUF_LEN;
len = MIN(pmsc->blk_len, MSC_MAX_DATA_BUF_LEN);
if( msc_disk_read(lun, pmsc->blk_addr, pmsc->data, len) != USB_OK)
{
bot_scsi_sense_code(udev, SENSE_KEY_HARDWARE_ERROR, MEDIUM_NOT_PRESENT);
return USB_FAIL;
}
usbd_ept_send(pudev, USBD_MSC_BULK_IN_EPT, pmsc->data, len);
pmsc->blk_addr += len;
pmsc->blk_len -= len;
pmsc->csw_struct.dCSWDataResidue -= len;
if(pmsc->blk_len == 0)
{
pmsc->msc_state = MSC_STATE_MACHINE_LAST_DATA;
}
return USB_OK;
}
/**
* @brief bulk-only transport scsi command write10
* @param udev: to the structure of usbd_core_type
* @param lun: logical units number
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_write10(void *udev, uint8_t lun)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
uint8_t *cmd = pmsc->cbw_struct.CBWCB;
uint32_t len;
if(pmsc->msc_state == MSC_STATE_MACHINE_IDLE)
{
if((pmsc->cbw_struct.bmCBWFlags & 0x80) == 0x80)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
return USB_FAIL;
}
pmsc->blk_addr = cmd[2] << 24 | cmd[3] << 16 | cmd[4] << 8 | cmd[5];
pmsc->blk_len = cmd[7] << 8 | cmd[8];
if(bot_scsi_check_address(udev, lun, pmsc->blk_addr, pmsc->blk_len) != USB_OK)
{
return USB_FAIL;
}
pmsc->blk_addr *= pmsc->blk_size[lun];
pmsc->blk_len *= pmsc->blk_size[lun];
if(pmsc->cbw_struct.dCBWDataTransferLength != pmsc->blk_len)
{
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
return USB_FAIL;
}
pmsc->msc_state = MSC_STATE_MACHINE_DATA_OUT;
len = MIN(pmsc->blk_len, MSC_MAX_DATA_BUF_LEN);
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT, (uint8_t *)pmsc->data, len);
}
else
{
len = MIN(pmsc->blk_len, MSC_MAX_DATA_BUF_LEN);
if(msc_disk_write(lun, pmsc->blk_addr, pmsc->data, len) != USB_OK)
{
bot_scsi_sense_code(udev, SENSE_KEY_HARDWARE_ERROR, MEDIUM_NOT_PRESENT);
return USB_FAIL;
}
pmsc->blk_addr += len;
pmsc->blk_len -= len;
pmsc->csw_struct.dCSWDataResidue -= len;
if(pmsc->blk_len == 0)
{
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_PASS);
}
else
{
len = MIN(pmsc->blk_len, MSC_MAX_DATA_BUF_LEN);
usbd_ept_recv(pudev, USBD_MSC_BULK_OUT_EPT, (uint8_t *)pmsc->data, len);
}
}
return USB_OK;
}
/**
* @brief clear feature
* @param udev: to the structure of usbd_core_type
* @param etp_num: endpoint number
* @retval status of usb_sts_type
*/
void bot_scsi_clear_feature(void *udev, uint8_t ept_num)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
if(pmsc->bot_status == MSC_BOT_STATE_ERROR)
{
usbd_set_stall(pudev, USBD_MSC_BULK_IN_EPT);
pmsc->bot_status = MSC_BOT_STATE_IDLE;
}
else if(((ept_num & 0x80) == 0x80) && (pmsc->bot_status != MSC_BOT_STATE_RECOVERY))
{
bot_scsi_send_csw(udev, CSW_BCSWSTATUS_FAILED);
}
}
/**
* @brief bulk-only transport scsi command process
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
usb_sts_type bot_scsi_cmd_process(void *udev)
{
usb_sts_type status = USB_FAIL;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
switch(pmsc->cbw_struct.CBWCB[0])
{
case MSC_CMD_INQUIRY:
status = bot_scsi_inquiry(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_START_STOP:
status = bot_scsi_start_stop(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_MODE_SENSE6:
status = bot_scsi_mode_sense6(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_MODE_SENSE10:
status = bot_scsi_mode_sense10(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_ALLOW_MEDIUM_REMOVAL:
status = bot_scsi_allow_medium_removal(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_READ_10:
status = bot_scsi_read10(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_READ_CAPACITY:
status = bot_scsi_capacity(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_REQUEST_SENSE:
status = bot_scsi_request_sense(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_TEST_UNIT:
status = bot_scsi_test_unit(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_VERIFY:
status = bot_scsi_verify(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_WRITE_10:
status = bot_scsi_write10(udev, pmsc->cbw_struct.bCBWLUN);
break;
case MSC_CMD_READ_FORMAT_CAPACITY:
status = bot_scsi_format_capacity(udev, pmsc->cbw_struct.bCBWLUN);
break;
default:
bot_scsi_sense_code(udev, SENSE_KEY_ILLEGAL_REQUEST, INVALID_COMMAND);
status = USB_FAIL;
break;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file msc_bot_scsi.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb mass storage bulk-only transport and scsi command header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __MSC_BOT_SCSI_H
#define __MSC_BOT_SCSI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "msc_class.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_msc_bot_scsi
* @{
*/
/** @defgroup USB_msc_bot_scsi_definition
* @{
*/
#define MSC_SUPPORT_MAX_LUN 1
#define MSC_MAX_DATA_BUF_LEN 4096
#define MSC_CMD_FORMAT_UNIT 0x04
#define MSC_CMD_INQUIRY 0x12
#define MSC_CMD_START_STOP 0x1B
#define MSC_CMD_MODE_SENSE6 0x1A
#define MSC_CMD_MODE_SENSE10 0x5A
#define MSC_CMD_ALLOW_MEDIUM_REMOVAL 0x1E
#define MSC_CMD_READ_10 0x28
#define MSC_CMD_READ_12 0xA8
#define MSC_CMD_READ_CAPACITY 0x25
#define MSC_CMD_READ_FORMAT_CAPACITY 0x23
#define MSC_CMD_REQUEST_SENSE 0x03
#define MSC_CMD_TEST_UNIT 0x00
#define MSC_CMD_VERIFY 0x2F
#define MSC_CMD_WRITE_10 0x2A
#define MSC_CMD_WRITE_12 0xAA
#define MSC_CMD_WRITE_VERIFY 0x2E
#define MSC_REQ_GET_MAX_LUN 0xFE /*!< get max lun */
#define MSC_REQ_BO_RESET 0xFF /*!< bulk only mass storage reset */
#define SET_LINE_CODING 0x20
#define GET_LINE_CODING 0x21
#define CBW_CMD_LENGTH 31
#define CBW_DCBWSIGNATURE 0x43425355
#define CBW_BMCBWFLAGS_DIR_OUT 0x00
#define CBW_BMCBWFLAGS_DIR_IN 0x80
#define CSW_CMD_LENGTH 13
#define CSW_DCSWSIGNATURE 0x53425355
#define CSW_BCSWSTATUS_PASS 0x00
#define CSW_BCSWSTATUS_FAILED 0x01
#define CSW_BCSWSTATUS_PHASE_ERR 0x02
#define MSC_STATE_MACHINE_CMD 0x00
#define MSC_STATE_MACHINE_DATA_IN 0x01
#define MSC_STATE_MACHINE_DATA_OUT 0x02
#define MSC_STATE_MACHINE_SEND_DATA 0x03
#define MSC_STATE_MACHINE_LAST_DATA 0x04
#define MSC_STATE_MACHINE_STATUS 0x05
#define MSC_STATE_MACHINE_FAILED 0x06
#define MSC_STATE_MACHINE_IDLE 0x07
#define MSC_BOT_STATE_IDLE 0x00
#define MSC_BOT_STATE_RECOVERY 0x01
#define MSC_BOT_STATE_ERROR 0x02
#define REQ_SENSE_STANDARD_DATA_LEN 0x12
#define SENSE_KEY_NO_SENSE 0x00
#define SENSE_KEY_RECOVERED_ERROR 0x01
#define SENSE_KEY_NOT_READY 0x02
#define SENSE_KEY_MEDIUM_ERROR 0x03
#define SENSE_KEY_HARDWARE_ERROR 0x04
#define SENSE_KEY_ILLEGAL_REQUEST 0x05
#define SENSE_KEY_UNIT_ATTENTION 0x06
#define SENSE_KEY_DATA_PROTECT 0x07
#define SENSE_KEY_BLANK_CHECK 0x08
#define SENSE_KEY_VENDERO_SPECIFIC 0x09
#define SENSE_KEY_ABORTED_COMMAND 0x0B
#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
#define SENSE_KEY_MISCOMPARE 0x0E
#define INVALID_COMMAND 0x20
#define INVALID_FIELED_IN_COMMAND 0x24
#define PARAMETER_LIST_LENGTH_ERROR 0x1A
#define INVALID_FIELD_IN_PARAMETER_LIST 0x26
#define ADDRESS_OUT_OF_RANGE 0x21
#define MEDIUM_NOT_PRESENT 0x3A
#define MEDIUM_HAVE_CHANGED 0x28
#define SCSI_INQUIRY_DATA_LENGTH 36
/**
* @brief typical command block description
*/
typedef struct
{
uint8_t opcode;
uint8_t lun;
uint32_t address;
uint8_t reserved1;
uint32_t alloc_length;
uint16_t reserved2;
}cbd_typical_type;
/**
* @brief extended command block description
*/
typedef struct
{
uint8_t opcode;
uint8_t lun;
uint32_t address;
uint8_t reserved1;
uint32_t alloc_length;
uint16_t reserved2;
}cbd_extended_type;
/**
* @brief command block wrapper
*/
typedef struct
{
uint32_t dCBWSignature;
uint32_t dCBWTage;
uint32_t dCBWDataTransferLength;
uint8_t bmCBWFlags;
uint8_t bCBWLUN;
uint8_t bCBWCBLength;
uint8_t CBWCB[16];
}cbw_type;
/**
* @brief command block wrapper
*/
typedef struct
{
uint32_t dCSWSignature;
uint32_t dCSWTag;
uint32_t dCSWDataResidue;
uint32_t bCSWStatus;
}csw_type;
/**
* @brief request sense standard data
*/
typedef struct
{
uint8_t err_code;
uint8_t reserved1;
uint8_t sense_key;
uint32_t information;
uint8_t as_length;
uint32_t reserved2;
uint8_t asc;
uint8_t ascq;
uint32_t reserved3;
}sense_type;
typedef struct
{
uint8_t msc_state;
uint8_t bot_status;
uint32_t max_lun;
uint32_t blk_nbr[MSC_SUPPORT_MAX_LUN];
uint32_t blk_size[MSC_SUPPORT_MAX_LUN];
uint32_t blk_addr;
uint32_t blk_len;
uint32_t data_len;
uint8_t data[MSC_MAX_DATA_BUF_LEN];
uint32_t alt_setting;
cbw_type cbw_struct;
csw_type csw_struct;
}msc_type;
void bot_scsi_init(void *udev);
void bot_scsi_reset(void *udev);
void bot_scsi_datain_handler(void *pudev, uint8_t ept_num);
void bot_scsi_dataout_handler(void *pudev, uint8_t ept_num);
void bot_cbw_decode(void *udev);
void bot_scsi_send_data(void *udev, uint8_t *buffer, uint32_t len);
void bot_scsi_send_csw(void *udev, uint8_t status);
void bot_scsi_sense_code(void *udev, uint8_t sense_key, uint8_t asc);
usb_sts_type bot_scsi_check_address(void *udev, uint8_t lun, uint32_t blk_offset, uint32_t blk_count);
void bot_scsi_stall(void *udev);
usb_sts_type bot_scsi_cmd_process(void *udev);
usb_sts_type bot_scsi_test_unit(void *udev, uint8_t lun);
usb_sts_type bot_scsi_inquiry(void *udev, uint8_t lun);
usb_sts_type bot_scsi_start_stop(void *udev, uint8_t lun);
usb_sts_type bot_scsi_allow_medium_removal(void *udev, uint8_t lun);
usb_sts_type bot_scsi_mode_sense6(void *udev, uint8_t lun);
usb_sts_type bot_scsi_mode_sense10(void *udev, uint8_t lun);
usb_sts_type bot_scsi_read10(void *udev, uint8_t lun);
usb_sts_type bot_scsi_capacity(void *udev, uint8_t lun);
usb_sts_type bot_scsi_format_capacity(void *udev, uint8_t lun);
usb_sts_type bot_scsi_request_sense(void *udev, uint8_t lun);
usb_sts_type bot_scsi_verify(void *udev, uint8_t lun);
usb_sts_type bot_scsi_write10(void *udev, uint8_t lun);
void bot_scsi_clear_feature(void *udev, uint8_t ept_num);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file msc_class.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb msc class type
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usbd_core.h"
#include "msc_class.h"
#include "msc_desc.h"
#include "msc_bot_scsi.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_msc_class
* @brief usb device class msc demo
* @{
*/
/** @defgroup USB_msc_class_private_functions
* @{
*/
static usb_sts_type class_init_handler(void *udev);
static usb_sts_type class_clear_handler(void *udev);
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup);
static usb_sts_type class_ept0_tx_handler(void *udev);
static usb_sts_type class_ept0_rx_handler(void *udev);
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num);
static usb_sts_type class_sof_handler(void *udev);
static usb_sts_type class_event_handler(void *udev, usbd_event_type event);
msc_type msc_struct;
/* usb device class handler */
usbd_class_handler msc_class_handler =
{
class_init_handler,
class_clear_handler,
class_setup_handler,
class_ept0_tx_handler,
class_ept0_rx_handler,
class_in_handler,
class_out_handler,
class_sof_handler,
class_event_handler,
&msc_struct
};
/**
* @brief initialize usb endpoint
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_init_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* open in endpoint */
usbd_ept_open(pudev, USBD_MSC_BULK_IN_EPT, EPT_BULK_TYPE, USBD_OUT_MAXPACKET_SIZE);
/* open out endpoint */
usbd_ept_open(pudev, USBD_MSC_BULK_OUT_EPT, EPT_BULK_TYPE, USBD_OUT_MAXPACKET_SIZE);
bot_scsi_init(udev);
return status;
}
/**
* @brief clear endpoint or other state
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_clear_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* close in endpoint */
usbd_ept_close(pudev, USBD_MSC_BULK_IN_EPT);
/* close out endpoint */
usbd_ept_close(pudev, USBD_MSC_BULK_OUT_EPT);
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: to the structure of usbd_core_type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
static usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
msc_type *pmsc = (msc_type *)pudev->class_handler->pdata;
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
{
/* class request */
case USB_REQ_TYPE_CLASS:
switch(setup->bRequest)
{
case MSC_REQ_GET_MAX_LUN:
usbd_ctrl_send(pudev, (uint8_t *)&pmsc->max_lun, 1);
break;
case MSC_REQ_BO_RESET:
bot_scsi_reset(udev);
usbd_ctrl_send_status(pudev);
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
/* standard request */
case USB_REQ_TYPE_STANDARD:
switch(setup->bRequest)
{
case USB_STD_REQ_GET_DESCRIPTOR:
usbd_ctrl_unsupport(pudev);
break;
case USB_STD_REQ_GET_INTERFACE:
usbd_ctrl_send(pudev, (uint8_t *)&pmsc->alt_setting, 1);
break;
case USB_STD_REQ_SET_INTERFACE:
pmsc->alt_setting = setup->wValue;
break;
case USB_STD_REQ_CLEAR_FEATURE:
usbd_ept_close(pudev, (uint8_t)setup->wIndex);
if((setup->wIndex & 0x80) == 0x80)
{
usbd_flush_tx_fifo(pudev, setup->wIndex & 0x7F);
usbd_ept_open(pudev, (uint8_t)setup->wIndex, EPT_BULK_TYPE, USBD_IN_MAXPACKET_SIZE);
}
else
{
usbd_ept_open(pudev, (uint8_t)setup->wIndex, EPT_BULK_TYPE, USBD_OUT_MAXPACKET_SIZE);
}
bot_scsi_clear_feature(udev, setup->wIndex);
break;
default:
break;
}
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
return status;
}
/**
* @brief usb device endpoint 0 in status stage complete
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_tx_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
UNUSED(udev);
return status;
}
/**
* @brief usb device endpoint 0 out status stage complete
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
static usb_sts_type class_ept0_rx_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
uint32_t recv_len = usbd_get_recv_len(pudev, 0);
/* ...user code... */
UNUSED(recv_len);
return status;
}
/**
* @brief usb device transmision complete handler
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
usbd_flush_tx_fifo(pudev, ept_num&0x7F);
bot_scsi_datain_handler(udev, ept_num);
return status;
}
/**
* @brief usb device endpoint receive data
* @param udev: to the structure of usbd_core_type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
static usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
bot_scsi_dataout_handler(udev, ept_num);
return status;
}
/**
* @brief usb device sof handler
* @param udev: to the structure of usbd_core_type
* @retval status of usb_sts_type
*/
static usb_sts_type class_sof_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
UNUSED(udev);
return status;
}
/**
* @brief usb device event handler
* @param udev: to the structure of usbd_core_type
* @param event: usb device event
* @retval status of usb_sts_type
*/
static usb_sts_type class_event_handler(void *udev, usbd_event_type event)
{
UNUSED(udev);
usb_sts_type status = USB_OK;
switch(event)
{
case USBD_RESET_EVENT:
/* ...user code... */
break;
case USBD_SUSPEND_EVENT:
/* ...user code... */
break;
case USBD_WAKEUP_EVENT:
/* ...user code... */
break;
default:
break;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

72
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/**
**************************************************************************
* @file msc_class.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb msc class file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __MSC_CLASS_H
#define __MSC_CLASS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "usb_std.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_msc_class
* @{
*/
/** @defgroup USB_msc_class_definition
* @{
*/
#define USBD_MSC_BULK_IN_EPT 0x81
#define USBD_MSC_BULK_OUT_EPT 0x01
#define USBD_IN_MAXPACKET_SIZE 0x40
#define USBD_OUT_MAXPACKET_SIZE 0x40
extern usbd_class_handler msc_class_handler;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file msc_desc.c
* @version v2.1.0
* @date 2022-08-16
* @brief usb msc device descriptor
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "stdio.h"
#include "usb_std.h"
#include "usbd_sdr.h"
#include "usbd_core.h"
#include "msc_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_msc_desc
* @brief usb device msc descriptor
* @{
*/
/** @defgroup USB_msc_desc_private_functions
* @{
*/
static usbd_desc_t *get_device_descriptor(void);
static usbd_desc_t *get_device_qualifier(void);
static usbd_desc_t *get_device_configuration(void);
static usbd_desc_t *get_device_other_speed(void);
static usbd_desc_t *get_device_lang_id(void);
static usbd_desc_t *get_device_manufacturer_string(void);
static usbd_desc_t *get_device_product_string(void);
static usbd_desc_t *get_device_serial_string(void);
static usbd_desc_t *get_device_interface_string(void);
static usbd_desc_t *get_device_config_string(void);
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
/**
* @brief device descriptor handler structure
*/
usbd_desc_handler msc_desc_handler =
{
get_device_descriptor,
get_device_qualifier,
get_device_configuration,
get_device_other_speed,
get_device_lang_id,
get_device_manufacturer_string,
get_device_product_string,
get_device_serial_string,
get_device_interface_string,
get_device_config_string,
};
/**
* @brief usb device standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
0x00, /* bcdUSB */
0x02,
0x00, /* bDeviceClass */
0x00, /* bDeviceSubClass */
0x00, /* bDeviceProtocol */
USB_MAX_EP0_SIZE, /* bMaxPacketSize */
LBYTE(USBD_MSC_VENDOR_ID), /* idVendor */
HBYTE(USBD_MSC_VENDOR_ID), /* idVendor */
LBYTE(USBD_MSC_PRODUCT_ID), /* idProduct */
HBYTE(USBD_MSC_PRODUCT_ID), /* idProduct */
0x00, /* bcdDevice rel. 2.00 */
0x02,
USB_MFC_STRING, /* Index of manufacturer string */
USB_PRODUCT_STRING, /* Index of product string */
USB_SERIAL_STRING, /* Index of serial number string */
1 /* bNumConfigurations */
};
/**
* @brief usb configuration standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_usbd_configuration[USBD_MSC_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
LBYTE(USBD_MSC_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
HBYTE(USBD_MSC_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
0x01, /* bNumInterfaces: 2 interface */
0x01, /* bConfigurationValue: configuration value */
0x04, /* iConfiguration: index of string descriptor describing
the configuration */
0xC0, /* bmAttributes: self powered */
0x32, /* MaxPower 100 mA: this current is used for detecting vbus */
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
0x00, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x02, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_MSC, /* bInterfaceClass: msc class code */
0x06, /* bInterfaceSubClass: subclass code scsi */
0x50, /* bInterfaceProtocol: protocol code BBB */
0x05, /* iInterface: index of string descriptor */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_MSC_BULK_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
LBYTE(USBD_IN_MAXPACKET_SIZE),
HBYTE(USBD_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
0x00, /* bInterval: interval for polling endpoint for data transfers */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_MSC_BULK_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
LBYTE(USBD_OUT_MAXPACKET_SIZE),
HBYTE(USBD_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
0x00, /* bInterval: interval for polling endpoint for data transfers */
};
/**
* @brief usb string lang id
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_lang_id[USBD_MSC_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_MSC_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
0x09,
0x04,
};
/**
* @brief usb string serial
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD static uint8_t g_string_serial[USBD_MSC_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_MSC_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,
};
/* device descriptor */
static usbd_desc_t device_descriptor =
{
USB_DEVICE_DESC_LEN,
g_usbd_descriptor
};
/* config descriptor */
static usbd_desc_t config_descriptor =
{
USBD_MSC_CONFIG_DESC_SIZE,
g_usbd_configuration
};
/* langid descriptor */
static usbd_desc_t langid_descriptor =
{
USBD_MSC_SIZ_STRING_LANGID,
g_string_lang_id
};
/* serial descriptor */
static usbd_desc_t serial_descriptor =
{
USBD_MSC_SIZ_STRING_SERIAL,
g_string_serial
};
static usbd_desc_t vp_desc;
/**
* @brief standard usb unicode convert
* @param string: source string
* @param unicode_buf: unicode buffer
* @retval length
*/
static uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf)
{
uint16_t str_len = 0, id_pos = 2;
uint8_t *tmp_str = string;
while(*tmp_str != '\0')
{
str_len ++;
unicode_buf[id_pos ++] = *tmp_str ++;
unicode_buf[id_pos ++] = 0x00;
}
str_len = str_len * 2 + 2;
unicode_buf[0] = (uint8_t)str_len;
unicode_buf[1] = USB_DESCIPTOR_TYPE_STRING;
return str_len;
}
/**
* @brief usb int convert to unicode
* @param value: int value
* @param pbus: unicode buffer
* @param len: length
* @retval none
*/
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len)
{
uint8_t idx = 0;
for( idx = 0 ; idx < len ; idx ++)
{
if( ((value >> 28)) < 0xA )
{
pbuf[ 2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/**
* @brief usb get serial number
* @param none
* @retval none
*/
static void get_serial_num(void)
{
uint32_t serial0, serial1, serial2;
serial0 = *(uint32_t*)MCU_ID1;
serial1 = *(uint32_t*)MCU_ID2;
serial2 = *(uint32_t*)MCU_ID3;
serial0 += serial2;
if (serial0 != 0)
{
usbd_int_to_unicode (serial0, &g_string_serial[2] ,8);
usbd_int_to_unicode (serial1, &g_string_serial[18] ,4);
}
}
/**
* @brief get device descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_descriptor(void)
{
return &device_descriptor;
}
/**
* @brief get device qualifier
* @param none
* @retval usbd_desc
*/
static usbd_desc_t * get_device_qualifier(void)
{
return NULL;
}
/**
* @brief get config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_configuration(void)
{
return &config_descriptor;
}
/**
* @brief get other speed descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_other_speed(void)
{
return NULL;
}
/**
* @brief get lang id descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_lang_id(void)
{
return &langid_descriptor;
}
/**
* @brief get manufacturer descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_manufacturer_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_MSC_DESC_MANUFACTURER_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get product descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_product_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_MSC_DESC_PRODUCT_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get serial descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_serial_string(void)
{
get_serial_num();
return &serial_descriptor;
}
/**
* @brief get interface descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_interface_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_MSC_DESC_INTERFACE_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get device config descriptor
* @param none
* @retval usbd_desc
*/
static usbd_desc_t *get_device_config_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_MSC_DESC_CONFIGURATION_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file msc_desc.h
* @version v2.1.0
* @date 2022-08-16
* @brief usb msc descriptor header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __MSC_DESC_H
#define __MSC_DESC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "msc_class.h"
#include "usbd_core.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_msc_desc
* @{
*/
/** @defgroup USB_msc_desc_definition
* @{
*/
#define MSC_BCD_NUM 0x0110
#define USBD_MSC_VENDOR_ID 0x2E3C
#define USBD_MSC_PRODUCT_ID 0x5720
#define USBD_MSC_CONFIG_DESC_SIZE 32
#define USBD_MSC_SIZ_STRING_LANGID 4
#define USBD_MSC_SIZ_STRING_SERIAL 0x1A
#define USBD_MSC_DESC_MANUFACTURER_STRING "Artery"
#define USBD_MSC_DESC_PRODUCT_STRING "AT32 Mass Storage"
#define USBD_MSC_DESC_CONFIGURATION_STRING "Mass Storage Config"
#define USBD_MSC_DESC_INTERFACE_STRING "Mass Storage Interface"
#define MCU_ID1 (0x1FFFF7E8)
#define MCU_ID2 (0x1FFFF7EC)
#define MCU_ID3 (0x1FFFF7F0)
extern usbd_desc_handler msc_desc_handler;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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