mirror of
https://github.com/iNavFlight/inav.git
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add support for at32 chips
Co-Authored-By: EMSR <10240646+shanggl@users.noreply.github.com> Co-Authored-By: carl <101383042+tcdddd@users.noreply.github.com> Co-Authored-By: Hugo Chiang <hugo@gyroflow.xyz>
This commit is contained in:
EMSR
Hugo Chiang
parent
389e9e9bc8
commit
a502106ddc
54 changed files with 7971 additions and 213 deletions
409
src/main/drivers/timer_impl_stdperiph_at32.c
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409
src/main/drivers/timer_impl_stdperiph_at32.c
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@ -0,0 +1,409 @@
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/*
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* This file is part of INAV.
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*
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* INAV is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* INAV is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with INAV. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <math.h>
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#include "platform.h"
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#include "build/atomic.h"
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#include "build/debug.h"
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#include "common/utils.h"
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#include "drivers/io.h"
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#include "drivers/rcc.h"
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#include "drivers/time.h"
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#include "drivers/nvic.h"
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#include "drivers/dma.h"
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#include "drivers/timer.h"
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#include "drivers/timer_impl.h"
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const uint16_t lookupDMASourceTable[4] = { TMR_C1_DMA_REQUEST, TMR_C2_DMA_REQUEST, TMR_C3_DMA_REQUEST, TMR_C4_DMA_REQUEST };
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const uint8_t lookupTIMChannelTable[4] = { TMR_C1_FLAG, TMR_C2_FLAG, TMR_C3_FLAG, TMR_C4_FLAG };
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void impl_timerInitContext(timHardwareContext_t * timCtx)
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{
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(void)timCtx; // NoOp
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}
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// Configure the interrupt priority
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void impl_timerNVICConfigure(TCH_t * tch, int irqPriority)
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{
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if (tch->timCtx->timDef->irq) {
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nvic_irq_enable(tch->timCtx->timDef->irq, irqPriority, 0);
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}
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if (tch->timCtx->timDef->secondIrq) {
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nvic_irq_enable(tch->timCtx->timDef->secondIrq, irqPriority, 0);
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}
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}
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void impl_timerConfigBase(TCH_t * tch, uint16_t period, uint32_t hz)
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{
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tmr_type * tim = tch->timCtx->timDef->tim;
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tmr_base_init(tim, (period - 1) & 0xffff, lrintf((float)timerGetBaseClock(tch) / hz + 0.01f) - 1);
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tmr_clock_source_div_set(tim, TMR_CLOCK_DIV1);
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tmr_cnt_dir_set(tim, TMR_COUNT_UP); //Count up (default)
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}
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void impl_enableTimer(TCH_t * tch)
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{
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tmr_counter_enable(tch->timHw->tim, TRUE);
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}
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void impl_timerPWMStart(TCH_t * tch)
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{
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tmr_output_enable(tch->timHw->tim,TRUE);
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}
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void impl_timerEnableIT(TCH_t * tch, uint32_t interrupt)
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{
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tmr_interrupt_enable(tch->timHw->tim, interrupt, TRUE);
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}
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void impl_timerDisableIT(TCH_t * tch, uint32_t interrupt)
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{
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tmr_interrupt_enable(tch->timHw->tim, interrupt, FALSE);
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}
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void impl_timerClearFlag(TCH_t * tch, uint32_t flag)
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{
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tmr_flag_clear(tch->timHw->tim, flag);
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}
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// calculate input filter constant
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static unsigned getFilter(unsigned ticks)
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{
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static const unsigned ftab[16] = {
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1*1, // fDTS !
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1*2, 1*4, 1*8, // fCK_INT
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2*6, 2*8, // fDTS/2
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4*6, 4*8,
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8*6, 8*8,
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16*5, 16*6, 16*8,
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32*5, 32*6, 32*8
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};
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for (unsigned i = 1; i < ARRAYLEN(ftab); i++) {
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if (ftab[i] > ticks) {
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return i - 1;
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}
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}
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return 0x0f;
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}
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void impl_timerChConfigIC(TCH_t * tch, bool polarityRising, unsigned inputFilterTicks)
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{
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tmr_input_config_type tmr_input_config_struct;
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tmr_input_default_para_init(&tmr_input_config_struct);
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tmr_input_config_struct.input_channel_select = lookupTIMChannelTable[tch->timHw->channelIndex];
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tmr_input_config_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
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tmr_input_config_struct.input_polarity_select = polarityRising ? TMR_INPUT_RISING_EDGE:TMR_INPUT_FALLING_EDGE;
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tmr_input_config_struct.input_filter_value = getFilter(inputFilterTicks);
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tmr_input_channel_init(tch->timHw->tim,&tmr_input_config_struct,TMR_CHANNEL_INPUT_DIV_1);
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}
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void impl_timerCaptureCompareHandler(tmr_type *tim, timHardwareContext_t *timerCtx)
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{
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unsigned tim_status = tim->ists & tim->iden;
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while (tim_status) {
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// flags will be cleared by reading CCR in dual capture, make sure we call handler correctly
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// currrent order is highest bit first. Code should not rely on specific order (it will introduce race conditions anyway)
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unsigned bit = __builtin_clz(tim_status);
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unsigned mask = ~(0x80000000 >> bit);
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tim->ists = mask;
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tim_status &= mask;
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if (timerCtx) {
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switch (bit) {
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case __builtin_clz(TMR_OVF_INT): {
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const uint16_t capture = tim->pr;
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if (timerCtx->ch[0].cb && timerCtx->ch[0].cb->callbackOvr) {
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timerCtx->ch[0].cb->callbackOvr(&timerCtx->ch[0], capture);
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}
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if (timerCtx->ch[1].cb && timerCtx->ch[1].cb->callbackOvr) {
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timerCtx->ch[1].cb->callbackOvr(&timerCtx->ch[1], capture);
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}
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if (timerCtx->ch[2].cb && timerCtx->ch[2].cb->callbackOvr) {
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timerCtx->ch[2].cb->callbackOvr(&timerCtx->ch[2], capture);
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}
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if (timerCtx->ch[3].cb && timerCtx->ch[3].cb->callbackOvr) {
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timerCtx->ch[3].cb->callbackOvr(&timerCtx->ch[3], capture);
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}
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break;
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}
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case __builtin_clz(TMR_C1_INT):
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timerCtx->ch[0].cb->callbackEdge(&timerCtx->ch[0], tim->c1dt);
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break;
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case __builtin_clz(TMR_C2_INT):
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timerCtx->ch[1].cb->callbackEdge(&timerCtx->ch[1], tim->c2dt);
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break;
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case __builtin_clz(TMR_C3_INT):
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timerCtx->ch[2].cb->callbackEdge(&timerCtx->ch[2], tim->c3dt);
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break;
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case __builtin_clz(TMR_C4_INT):
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timerCtx->ch[3].cb->callbackEdge(&timerCtx->ch[3], tim->c4dt);
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break;
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}
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}
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else {
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// timerConfig == NULL
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volatile uint32_t tmp;
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switch (bit) {
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case __builtin_clz(TMR_OVF_INT):
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tmp = tim->pr;
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break;
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case __builtin_clz(TMR_C1_INT):
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tmp = tim->c1dt;
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break;
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case __builtin_clz(TMR_C2_INT):
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tmp = tim->c2dt;
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break;
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case __builtin_clz(TMR_C3_INT):
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tmp = tim->c3dt;
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break;
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case __builtin_clz(TMR_C4_INT):
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tmp = tim->c4dt;
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break;
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}
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(void)tmp;
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}
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}
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}
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void impl_timerPWMConfigChannel(TCH_t * tch, uint16_t value)
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{
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const bool inverted = tch->timHw->output & TIMER_OUTPUT_INVERTED;
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tmr_output_config_type tmr_output_struct;
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tmr_output_default_para_init(&tmr_output_struct);
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tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
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if (tch->timHw->output & TIMER_OUTPUT_N_CHANNEL) {
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tmr_output_struct.oc_output_state = FALSE;
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tmr_output_struct.occ_output_state = TRUE;
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tmr_output_struct.occ_polarity = inverted ? TMR_OUTPUT_ACTIVE_LOW : TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.occ_idle_state = FALSE;
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} else {
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tmr_output_struct.oc_output_state = TRUE;
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tmr_output_struct.occ_output_state = FALSE;
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tmr_output_struct.oc_polarity = inverted ? TMR_OUTPUT_ACTIVE_LOW : TMR_OUTPUT_ACTIVE_HIGH;
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tmr_output_struct.oc_idle_state = TRUE;
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}
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switch (tch->timHw->channelIndex) {
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case 0:
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tmr_output_channel_config(tch->timHw->tim,TMR_SELECT_CHANNEL_1, &tmr_output_struct);
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tmr_channel_value_set(tch->timHw->tim, TMR_SELECT_CHANNEL_1, value);
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tmr_output_channel_buffer_enable(tch->timHw->tim,TMR_SELECT_CHANNEL_1,TRUE);
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break;
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case 1:
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tmr_output_channel_config(tch->timHw->tim,TMR_SELECT_CHANNEL_2, &tmr_output_struct);
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tmr_channel_value_set(tch->timHw->tim, TMR_SELECT_CHANNEL_2, value);
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tmr_output_channel_buffer_enable(tch->timHw->tim,TMR_SELECT_CHANNEL_2,TRUE);
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break;
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case 2:
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tmr_output_channel_config(tch->timHw->tim,TMR_SELECT_CHANNEL_3, &tmr_output_struct);
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tmr_channel_value_set(tch->timHw->tim, TMR_SELECT_CHANNEL_3, value);
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tmr_output_channel_buffer_enable(tch->timHw->tim,TMR_SELECT_CHANNEL_3,TRUE);
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break;
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case 3:
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tmr_output_channel_config(tch->timHw->tim,TMR_SELECT_CHANNEL_4, &tmr_output_struct);
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tmr_channel_value_set(tch->timHw->tim, TMR_SELECT_CHANNEL_4, value);
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tmr_output_channel_buffer_enable(tch->timHw->tim,TMR_SELECT_CHANNEL_4,TRUE);
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break;
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}
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}
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volatile timCCR_t * impl_timerCCR(TCH_t * tch)
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{
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switch (tch->timHw->channelIndex) {
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case 0:
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return &tch->timHw->tim->c1dt;
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break;
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case 1:
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return &tch->timHw->tim->c2dt;
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break;
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case 2:
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return &tch->timHw->tim->c3dt;
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break;
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case 3:
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return &tch->timHw->tim->c4dt;
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break;
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}
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return NULL;
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}
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// Set the channel control register
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void impl_timerChCaptureCompareEnable(TCH_t * tch, bool enable)
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{
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tmr_channel_enable(tch->timHw->tim, lookupTIMChannelTable[tch->timHw->channelIndex],(enable ? TRUE : FALSE));
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}
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// lookupDMASourceTable
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static void impl_timerDMA_IRQHandler(DMA_t descriptor)
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{
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if (DMA_GET_FLAG_STATUS(descriptor, DMA_IT_TCIF)) {
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TCH_t * tch = (TCH_t *)descriptor->userParam;
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tch->dmaState = TCH_DMA_IDLE;
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dma_channel_enable(tch->dma->ref,FALSE);
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tmr_dma_request_enable(tch->timHw->tim, lookupDMASourceTable[tch->timHw->channelIndex], FALSE);
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DMA_CLEAR_FLAG(descriptor, DMA_IT_TCIF);
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}
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}
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bool impl_timerPWMConfigChannelDMA(TCH_t * tch, void * dmaBuffer, uint8_t dmaBufferElementSize, uint32_t dmaBufferElementCount)
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{
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dma_init_type dma_init_struct = {0};
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tmr_type * timer = tch->timHw->tim;
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tch->dma = dmaGetByTag(tch->timHw->dmaTag);
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if (tch->dma == NULL) {
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return false;
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}
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// If DMA is already in use - abort
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if (tch->dma->owner != OWNER_FREE) {
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return false;
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}
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// We assume that timer channels are already initialized by calls to
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tmr_output_enable(timer, TRUE);
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// enable The TMR periodic buffer register
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tmr_period_buffer_enable(timer,TRUE);
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tmr_channel_enable(timer, lookupTIMChannelTable[tch->timHw->channelIndex],TRUE);
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tmr_counter_enable(timer, TRUE);
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dmaInit(tch->dma, OWNER_TIMER, 0);
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dmaSetHandler(tch->dma, impl_timerDMA_IRQHandler, NVIC_PRIO_TIMER_DMA, (uint32_t)tch);
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dma_reset(tch->dma->ref);
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dma_channel_enable(tch->dma->ref,FALSE);
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dma_reset(tch->dma->ref);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.peripheral_base_addr = (uint32_t)impl_timerCCR(tch);
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dma_init_struct.buffer_size = dmaBufferElementCount;
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.loop_mode_enable = FALSE;
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switch (dmaBufferElementSize) {
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case 1:
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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break;
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case 2:
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
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break;
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case 4:
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_WORD;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_WORD;
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break;
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default:
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// Programmer error
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while(1) {
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}
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}
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dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
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dma_init_struct.memory_base_addr = (uint32_t)dmaBuffer;
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dma_init_struct.priority = DMA_PRIORITY_HIGH;
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dma_init(tch->dma->ref, &dma_init_struct);
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//Set DMA request Mux mapping
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dmaMuxEnable(tch->dma, tch->timHw->dmaMuxid);
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dma_interrupt_enable(tch->dma->ref, DMA_IT_TCIF, TRUE);
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return true;
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}
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void impl_timerPWMPrepareDMA(TCH_t * tch, uint32_t dmaBufferElementCount)
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{
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tch->dma = dmaGetByTag(tch->timHw->dmaTag);
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if (tch->dma == NULL) {
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return ;
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}
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// Make sure we terminate any DMA transaction currently in progress
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// Clear the flag as well, so even if DMA transfer finishes while within ATOMIC_BLOCK
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// the resulting IRQ won't mess up the DMA state
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ATOMIC_BLOCK(NVIC_PRIO_MAX) {
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dma_channel_enable(tch->dma->ref,FALSE);
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tmr_dma_request_enable(tch->timHw->tim, lookupDMASourceTable[tch->timHw->channelIndex], FALSE);
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// clear dma flag
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DMA_CLEAR_FLAG(tch->dma, DMA_IT_TCIF);
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}
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dma_data_number_set(tch->dma->ref, dmaBufferElementCount);
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dma_channel_enable(tch->dma->ref,TRUE);
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tch->dmaState = TCH_DMA_READY;
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}
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void impl_timerPWMStartDMA(TCH_t * tch)
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{
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uint16_t dmaSources = 0;
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timHardwareContext_t * timCtx = tch->timCtx;
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if (timCtx->ch[0].dmaState == TCH_DMA_READY) {
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timCtx->ch[0].dmaState = TCH_DMA_ACTIVE;
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dmaSources |= TMR_C1_DMA_REQUEST;
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}
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if (timCtx->ch[1].dmaState == TCH_DMA_READY) {
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timCtx->ch[1].dmaState = TCH_DMA_ACTIVE;
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dmaSources |= TMR_C2_DMA_REQUEST;
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}
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if (timCtx->ch[2].dmaState == TCH_DMA_READY) {
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timCtx->ch[2].dmaState = TCH_DMA_ACTIVE;
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dmaSources |= TMR_C3_DMA_REQUEST;
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}
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if (timCtx->ch[3].dmaState == TCH_DMA_READY) {
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timCtx->ch[3].dmaState = TCH_DMA_ACTIVE;
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dmaSources |= TMR_C4_DMA_REQUEST;
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}
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if (dmaSources) {
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tmr_counter_value_set(tch->timHw->tim, 0);
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tmr_dma_request_enable(tch->timHw->tim, dmaSources, TRUE);
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}
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}
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void impl_timerPWMStopDMA(TCH_t * tch)
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{
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dma_channel_enable(tch->dma->ref,FALSE);
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tmr_dma_request_enable(tch->timHw->tim, lookupDMASourceTable[tch->timHw->channelIndex], FALSE);
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tmr_counter_enable(tch->timHw->tim, TRUE);
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}
|
||||
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Add table
Add a link
Reference in a new issue