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Code Issues Wiki Activity

Removing Timer Usage Flags (#12862)

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This commit is contained in:
J Blackman 2023-06-07 06:49:13 +10:00 • committed by GitHub
parent d8a9906e92
commit 7d7b6596b0
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GPG key ID: 4AEE18F83AFDEB23
12 changed files with 419 additions and 463 deletions
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112
src/main/drivers/at32/timer_at32f43x.c
View file

@ -52,71 +52,71 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
#if defined(USE_TIMER_MGMT)
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Port A
DEF_TIM(TMR2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA0, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, 0, 0, 0),
// Port B ORDER BY MUX 1 2 3
//MUX1
DEF_TIM(TMR1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB0, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, 0, 0, 0),
//MUX2
DEF_TIM(TMR3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, TIM_USE_ANY, 0, 13, 9),
DEF_TIM(TMR4, CH2, PB7, TIM_USE_ANY, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, TIM_USE_ANY, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, TIM_USE_ANY, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH3, PB0, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, 0, 13, 9),
DEF_TIM(TMR4, CH2, PB7, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, 0, 0, 0),
//MUX3
DEF_TIM(TMR8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB0, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, 0, 0, 0),
// Port C ORDER BY MUX 1 2 3
//MUX2
DEF_TIM(TMR20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH2, PC7, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH2, PC2, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, 0, 0, 12),
DEF_TIM(TMR3, CH2, PC7, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, 0, 0, 0),
//MUX 3
DEF_TIM(TMR8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1, PC6, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, 0, 0, 0),
};
#endif

3
src/main/drivers/at32/timer_def.h
View file

@ -138,11 +138,10 @@
@dmaopt dma channel index used for timer channel data transmit
@upopt USE_DSHOT_DMAR timeup dma channel index
*/
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \

34
src/main/drivers/stm32/dshot_bitbang.c
View file

@ -101,16 +101,16 @@ FAST_DATA_ZERO_INIT timeUs_t dshotFrameUs;
const timerHardware_t bbTimerHardware[] = {
#if defined(STM32F4) || defined(STM32F7)
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH1, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH2, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH3, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH4, NONE, TIM_USE_NONE, 0, 0),
DEF_TIM(TIM8, CH1, NONE, 0, 1),
DEF_TIM(TIM8, CH2, NONE, 0, 1),
DEF_TIM(TIM8, CH3, NONE, 0, 1),
DEF_TIM(TIM8, CH4, NONE, 0, 0),
#endif
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 2),
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 0),
DEF_TIM(TIM1, CH1, NONE, 0, 1),
DEF_TIM(TIM1, CH1, NONE, 0, 2),
DEF_TIM(TIM1, CH2, NONE, 0, 1),
DEF_TIM(TIM1, CH3, NONE, 0, 1),
DEF_TIM(TIM1, CH4, NONE, 0, 0),
#elif defined(STM32G4) || defined(STM32H7)
// XXX TODO: STM32G4 and STM32H7 can use any timer for pacing
@ -121,14 +121,14 @@ const timerHardware_t bbTimerHardware[] = {
// 4 motors scattered across 4 different GPIO ports.
// - For hexas (and larger), more channels may become necessary,
// in which case the DMA request numbers should be modified.
DEF_TIM(TIM8, CH1, NONE, TIM_USE_NONE, 0, 0, 0),
DEF_TIM(TIM8, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
DEF_TIM(TIM8, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
DEF_TIM(TIM8, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 0, 0),
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
DEF_TIM(TIM8, CH1, NONE, 0, 0, 0),
DEF_TIM(TIM8, CH2, NONE, 0, 1, 0),
DEF_TIM(TIM8, CH3, NONE, 0, 2, 0),
DEF_TIM(TIM8, CH4, NONE, 0, 3, 0),
DEF_TIM(TIM1, CH1, NONE, 0, 0, 0),
DEF_TIM(TIM1, CH2, NONE, 0, 1, 0),
DEF_TIM(TIM1, CH3, NONE, 0, 2, 0),
DEF_TIM(TIM1, CH4, NONE, 0, 3, 0),
#else
#error MCU dependent code required

12
src/main/drivers/stm32/timer_def.h
View file

@ -145,11 +145,10 @@
#if defined(STM32F4)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TIM_ ## tim) \
DEF_TIM_DMA_COND(/* add comma */ , \
@ -250,11 +249,10 @@
#define DEF_TIM_DMA__BTCH_TIM14_UP NONE
#elif defined(STM32F7)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
@ -476,11 +474,10 @@
#define DEF_TIM_AF__PI7__TCH_TIM8_CH3 D(3, 8)
#elif defined(STM32H7)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
@ -829,11 +826,10 @@
// Missing from FW1.0.0 library?
#define GPIO_AF12_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \

3
src/main/drivers/stm32/timer_hal.c
View file

@ -1031,9 +1031,6 @@ void timerInit(void)
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
for (unsigned timerIndex = 0; timerIndex < TIMER_CHANNEL_COUNT; timerIndex++) {
const timerHardware_t *timerHardwarePtr = &TIMER_HARDWARE[timerIndex];
if (timerHardwarePtr->usageFlags == TIM_USE_NONE) {
continue;
}
// XXX IOConfigGPIOAF in timerInit should eventually go away.
IOConfigGPIOAF(IOGetByTag(timerHardwarePtr->tag), IOCFG_AF_PP, timerHardwarePtr->alternateFunction);
}

166
src/main/drivers/stm32/timer_stm32f4xx.c
View file

@ -60,129 +60,129 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Auto-generated from 'timer_def.h'
//PORTA
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, 0, 0),
DEF_TIM(TIM2, CH3, PA2, 0, 0),
DEF_TIM(TIM2, CH4, PA3, 0, 0),
DEF_TIM(TIM2, CH1, PA5, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, 0, 0),
DEF_TIM(TIM1, CH1, PA8, 0, 0),
DEF_TIM(TIM1, CH2, PA9, 0, 0),
DEF_TIM(TIM1, CH3, PA10, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, 0, 0),
DEF_TIM(TIM2, CH1, PA15, 0, 0),
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH1, PA0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, 0, 0),
DEF_TIM(TIM5, CH3, PA2, 0, 0),
DEF_TIM(TIM5, CH4, PA3, 0, 0),
DEF_TIM(TIM3, CH1, PA6, 0, 0),
DEF_TIM(TIM3, CH2, PA7, 0, 0),
DEF_TIM(TIM9, CH1, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH2, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH1, PA2, 0, 0),
DEF_TIM(TIM9, CH2, PA3, 0, 0),
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1N, PA5, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, 0, 0),
DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM13, CH1, PA6, 0, 0),
DEF_TIM(TIM14, CH1, PA7, 0, 0),
#endif
//PORTB
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PB0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, 0, 0),
DEF_TIM(TIM2, CH2, PB3, 0, 0),
DEF_TIM(TIM2, CH3, PB10, 0, 0),
DEF_TIM(TIM2, CH4, PB11, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, 0, 0),
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH3, PB0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, 0, 0),
DEF_TIM(TIM3, CH1, PB4, 0, 0),
DEF_TIM(TIM3, CH2, PB5, 0, 0),
DEF_TIM(TIM4, CH1, PB6, 0, 0),
DEF_TIM(TIM4, CH2, PB7, 0, 0),
DEF_TIM(TIM4, CH3, PB8, 0, 0),
DEF_TIM(TIM4, CH4, PB9, 0, 0),
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2N, PB0, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, 0, 0),
#endif
DEF_TIM(TIM10, CH1, PB8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM11, CH1, PB9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM10, CH1, PB8, 0, 0),
DEF_TIM(TIM11, CH1, PB9, 0, 0),
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH2N, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3N, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2N, PB14, 0, 0),
DEF_TIM(TIM8, CH3N, PB15, 0, 0),
DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM12, CH1, PB14, 0, 0),
DEF_TIM(TIM12, CH2, PB15, 0, 0),
#endif
//PORTC
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PC6, 0, 0),
DEF_TIM(TIM3, CH2, PC7, 0, 0),
DEF_TIM(TIM3, CH3, PC8, 0, 0),
DEF_TIM(TIM3, CH4, PC9, 0, 0),
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1, PC6, 0, 0),
DEF_TIM(TIM8, CH2, PC7, 0, 0),
DEF_TIM(TIM8, CH3, PC8, 0, 0),
DEF_TIM(TIM8, CH4, PC9, 0, 0),
#endif
//PORTD
DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH1, PD12, 0, 0),
DEF_TIM(TIM4, CH2, PD13, 0, 0),
DEF_TIM(TIM4, CH3, PD14, 0, 0),
DEF_TIM(TIM4, CH4, PD15, 0, 0),
//PORTE
DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PE8, 0, 0),
DEF_TIM(TIM1, CH1, PE9, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, 0, 0),
DEF_TIM(TIM1, CH2, PE11, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, 0, 0),
DEF_TIM(TIM1, CH3, PE13, 0, 0),
DEF_TIM(TIM1, CH4, PE14, 0, 0),
DEF_TIM(TIM9, CH1, PE5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH2, PE6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH1, PE5, 0, 0),
DEF_TIM(TIM9, CH2, PE6, 0, 0),
//PORTF
#if !defined(STM32F411xE)
DEF_TIM(TIM10, CH1, PF6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM11, CH1, PF7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM10, CH1, PF6, 0, 0),
DEF_TIM(TIM11, CH1, PF7, 0, 0),
#endif
//PORTH
// Port H is not available for LPQFP-100 or 144 package
// DEF_TIM(TIM5, CH1, PH10, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH1, PH10, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, 0, 0),
//
//#if !defined(STM32F411xE)
// DEF_TIM(TIM8, CH1N, PH13, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH1N, PH13, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, 0, 0),
//
// DEF_TIM(TIM12, CH1, PH6, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM12, CH1, PH6, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, 0, 0),
//#endif
//PORTI
// Port I is not available for LPQFP-100 or 144 package
// DEF_TIM(TIM5, CH4, PI0, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH4, PI0, 0, 0),
//
//#if !defined(STM32F411xE)
// DEF_TIM(TIM8, CH4, PI2, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH1, PI5, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH2, PI6, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH3, PI7, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH4, PI2, 0, 0),
// DEF_TIM(TIM8, CH1, PI5, 0, 0),
// DEF_TIM(TIM8, CH2, PI6, 0, 0),
// DEF_TIM(TIM8, CH3, PI7, 0, 0),
//#endif
};
#endif

166
src/main/drivers/stm32/timer_stm32f7xx.c
View file

@ -53,116 +53,116 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Auto-generated from 'timer_def.h'
//PORTA
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH1, PA0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, 0, 0),
DEF_TIM(TIM2, CH3, PA2, 0, 0),
DEF_TIM(TIM2, CH4, PA3, 0, 0),
DEF_TIM(TIM2, CH1, PA5, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, 0, 0),
DEF_TIM(TIM1, CH1, PA8, 0, 0),
DEF_TIM(TIM1, CH2, PA9, 0, 0),
DEF_TIM(TIM1, CH3, PA10, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, 0, 0),
DEF_TIM(TIM2, CH1, PA15, 0, 0),
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM5, CH1, PA0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, 0, 0),
DEF_TIM(TIM5, CH3, PA2, 0, 0),
DEF_TIM(TIM5, CH4, PA3, 0, 0),
DEF_TIM(TIM3, CH1, PA6, 0, 0),
DEF_TIM(TIM3, CH2, PA7, 0, 0),
DEF_TIM(TIM9, CH1, PA2, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH2, PA3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH1, PA2, 0, 0),
DEF_TIM(TIM9, CH2, PA3, 0, 0),
DEF_TIM(TIM8, CH1N, PA5, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, 0, 0),
DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM13, CH1, PA6, 0, 0),
DEF_TIM(TIM14, CH1, PA7, 0, 0),
//PORTB
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PB0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, 0, 0),
DEF_TIM(TIM2, CH2, PB3, 0, 0),
DEF_TIM(TIM2, CH3, PB10, 0, 0),
DEF_TIM(TIM2, CH4, PB11, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, 0, 0),
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH3, PB0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, 0, 0),
DEF_TIM(TIM3, CH1, PB4, 0, 0),
DEF_TIM(TIM3, CH2, PB5, 0, 0),
DEF_TIM(TIM4, CH1, PB6, 0, 0),
DEF_TIM(TIM4, CH2, PB7, 0, 0),
DEF_TIM(TIM4, CH3, PB8, 0, 0),
DEF_TIM(TIM4, CH4, PB9, 0, 0),
DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM10, CH1, PB8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM11, CH1, PB9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2N, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3N, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2N, PB0, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, 0, 0),
DEF_TIM(TIM10, CH1, PB8, 0, 0),
DEF_TIM(TIM11, CH1, PB9, 0, 0),
DEF_TIM(TIM8, CH2N, PB14, 0, 0),
DEF_TIM(TIM8, CH3N, PB15, 0, 0),
DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM12, CH1, PB14, 0, 0),
DEF_TIM(TIM12, CH2, PB15, 0, 0),
//PORTC
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM3, CH1, PC6, 0, 0),
DEF_TIM(TIM3, CH2, PC7, 0, 0),
DEF_TIM(TIM3, CH3, PC8, 0, 0),
DEF_TIM(TIM3, CH4, PC9, 0, 0),
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM8, CH1, PC6, 0, 0),
DEF_TIM(TIM8, CH2, PC7, 0, 0),
DEF_TIM(TIM8, CH3, PC8, 0, 0),
DEF_TIM(TIM8, CH4, PC9, 0, 0),
//PORTD
DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM4, CH1, PD12, 0, 0),
DEF_TIM(TIM4, CH2, PD13, 0, 0),
DEF_TIM(TIM4, CH3, PD14, 0, 0),
DEF_TIM(TIM4, CH4, PD15, 0, 0),
//PORTE
DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM1, CH1N, PE8, 0, 0),
DEF_TIM(TIM1, CH1, PE9, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, 0, 0),
DEF_TIM(TIM1, CH2, PE11, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, 0, 0),
DEF_TIM(TIM1, CH3, PE13, 0, 0),
DEF_TIM(TIM1, CH4, PE14, 0, 0),
DEF_TIM(TIM9, CH1, PE5, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH2, PE6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM9, CH1, PE5, 0, 0),
DEF_TIM(TIM9, CH2, PE6, 0, 0),
//PORTF
DEF_TIM(TIM10, CH1, PF6, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM11, CH1, PF7, TIM_USE_ANY, 0, 0),
DEF_TIM(TIM10, CH1, PF6, 0, 0),
DEF_TIM(TIM11, CH1, PF7, 0, 0),
//PORTH
// Port I is not available for LPQFP-100 or 144 package
// DEF_TIM(TIM5, CH1, PH10, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH1, PH10, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, 0, 0),
//
// DEF_TIM(TIM8, CH1N, PH13, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH1N, PH13, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, 0, 0),
//
// DEF_TIM(TIM12, CH1, PH6, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM12, CH1, PH6, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, 0, 0),
//PORTI
// Port I is not available for LPQFP-100 or 144 package
// DEF_TIM(TIM5, CH4, PI0, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM5, CH4, PI0, 0, 0),
//
// DEF_TIM(TIM8, CH4, PI2, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH1, PI5, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH2, PI6, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH3, PI7, TIM_USE_ANY, 0, 0),
// DEF_TIM(TIM8, CH4, PI2, 0, 0),
// DEF_TIM(TIM8, CH1, PI5, 0, 0),
// DEF_TIM(TIM8, CH2, PI6, 0, 0),
// DEF_TIM(TIM8, CH3, PI7, 0, 0),
};
#endif

186
src/main/drivers/stm32/timer_stm32g4xx.c
View file

@ -52,120 +52,120 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Auto-generated from 'timer_def.h'
// Port A
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PA12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PA13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA0, 0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA2, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA3, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA5, 0, 0, 0),
DEF_TIM(TIM16, CH1, PA6, 0, 0, 0),
DEF_TIM(TIM17, CH1, PA7, 0, 0, 0),
DEF_TIM(TIM16, CH1, PA12, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PA13, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA15, 0, 0, 0),
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH1, PA0, 0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, 0, 0, 0),
DEF_TIM(TIM5, CH3, PA2, 0, 0, 0),
DEF_TIM(TIM5, CH4, PA3, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA4, 0, 0, 0),
DEF_TIM(TIM3, CH1, PA6, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA7, 0, 0, 0),
DEF_TIM(TIM8, CH1, PA15, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, 0, 0, 0),
DEF_TIM(TIM8, CH2, PA14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2, PA14, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PA12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, 0, 0, 0),
DEF_TIM(TIM1, CH1, PA8, 0, 0, 0),
DEF_TIM(TIM1, CH2, PA9, 0, 0, 0),
DEF_TIM(TIM1, CH3, PA10, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA11, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PA12, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PA1, 0, 0, 0),
DEF_TIM(TIM15, CH1, PA2, 0, 0, 0),
DEF_TIM(TIM15, CH2, PA3, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH1, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH2, PA12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH3, PA13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA9, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA10, 0, 0, 0),
DEF_TIM(TIM4, CH1, PA11, 0, 0, 0),
DEF_TIM(TIM4, CH2, PA12, 0, 0, 0),
DEF_TIM(TIM4, CH3, PA13, 0, 0, 0),
DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH4, PA11, 0, 0, 0),
// Port B
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH2, PB3, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB4, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PB6, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PB7, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB8, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB9, 0, 0, 0),
DEF_TIM(TIM2, CH3, PB10, 0, 0, 0),
DEF_TIM(TIM2, CH4, PB11, 0, 0, 0),
DEF_TIM(TIM15, CH1, PB14, 0, 0, 0),
DEF_TIM(TIM15, CH2, PB15, 0, 0, 0),
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH3, PB0, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, 0, 0, 0),
DEF_TIM(TIM5, CH1, PB2, 0, 0, 0),
DEF_TIM(TIM3, CH1, PB4, 0, 0, 0),
DEF_TIM(TIM3, CH2, PB5, 0, 0, 0),
DEF_TIM(TIM4, CH1, PB6, 0, 0, 0),
DEF_TIM(TIM4, CH2, PB7, 0, 0, 0),
DEF_TIM(TIM4, CH3, PB8, 0, 0, 0),
DEF_TIM(TIM4, CH4, PB9, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PB15, 0, 0, 0),
DEF_TIM(TIM20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM20, CH1, PB2, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PB5, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PB0, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PB1, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PB3, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PB4, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, 0, 0, 0),
DEF_TIM(TIM8, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1, PB6, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB0, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB5, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB7, 0, 0, 0),
DEF_TIM(TIM8, CH2, PB8, 0, 0, 0),
DEF_TIM(TIM8, CH3, PB9, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB9, 0, 0, 0),
// Port C
DEF_TIM(TIM5, CH2, PC12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH2, PC12, 0, 0, 0),
DEF_TIM(TIM1, CH1, PC0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2, PC1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH4, PC3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1, PC0, 0, 0, 0),
DEF_TIM(TIM1, CH2, PC1, 0, 0, 0),
DEF_TIM(TIM1, CH3, PC2, 0, 0, 0),
DEF_TIM(TIM1, CH4, PC3, 0, 0, 0),
DEF_TIM(TIM3, CH1, PC6, 0, 0, 0),
DEF_TIM(TIM3, CH2, PC7, 0, 0, 0),
DEF_TIM(TIM3, CH3, PC8, 0, 0, 0),
DEF_TIM(TIM3, CH4, PC9, 0, 0, 0),
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PC10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PC11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PC12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PC13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1, PC6, 0, 0, 0),
DEF_TIM(TIM8, CH2, PC7, 0, 0, 0),
DEF_TIM(TIM8, CH3, PC8, 0, 0, 0),
DEF_TIM(TIM8, CH4, PC9, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PC10, 0, 0, 0),
DEF_TIM(TIM8, CH2N, PC11, 0, 0, 0),
DEF_TIM(TIM8, CH3N, PC12, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PC13, 0, 0, 0),
DEF_TIM(TIM20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH4N, PC5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM20, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH4N, PC13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM20, CH2, PC2, 0, 0, 0),
DEF_TIM(TIM1, CH4N, PC5, 0, 0, 0),
DEF_TIM(TIM20, CH3, PC8, 0, 0, 0),
DEF_TIM(TIM8, CH4N, PC13, 0, 0, 0),
};
#endif

164
src/main/drivers/stm32/timer_stm32h7xx.c
View file

@ -53,110 +53,110 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Auto-generated from 'timer_def.h'
// Port A
DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA0, 0, 0, 0),
DEF_TIM(TIM2, CH2, PA1, 0, 0, 0),
DEF_TIM(TIM2, CH3, PA2, 0, 0, 0),
DEF_TIM(TIM2, CH4, PA3, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA5, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PA7, 0, 0, 0),
DEF_TIM(TIM1, CH1, PA8, 0, 0, 0),
DEF_TIM(TIM1, CH2, PA9, 0, 0, 0),
DEF_TIM(TIM1, CH3, PA10, 0, 0, 0),
DEF_TIM(TIM1, CH4, PA11, 0, 0, 0),
DEF_TIM(TIM2, CH1, PA15, 0, 0, 0),
DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM5, CH1, PA0, 0, 0, 0),
DEF_TIM(TIM5, CH2, PA1, 0, 0, 0),
DEF_TIM(TIM5, CH3, PA2, 0, 0, 0),
DEF_TIM(TIM5, CH4, PA3, 0, 0, 0),
DEF_TIM(TIM3, CH1, PA6, 0, 0, 0),
DEF_TIM(TIM3, CH2, PA7, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA5, 0, 0, 0),
DEF_TIM(TIM8, CH1N, PA7, 0, 0, 0),
DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM13, CH1, PA6, 0, 0, 0),
DEF_TIM(TIM14, CH1, PA7, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PA1, 0, 0, 0),
DEF_TIM(TIM15, CH1, PA2, 0, 0, 0),
DEF_TIM(TIM15, CH2, PA3, 0, 0, 0),
// Port B
DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB0, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB1, 0, 0, 0),
DEF_TIM(TIM2, CH2, PB3, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PB6, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PB7, 0, 0, 0),
DEF_TIM(TIM16, CH1, PB8, 0, 0, 0),
DEF_TIM(TIM17, CH1, PB9, 0, 0, 0),
DEF_TIM(TIM2, CH3, PB10, 0, 0, 0),
DEF_TIM(TIM2, CH4, PB11, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PB13, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PB14, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PB15, 0, 0, 0),
DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH3, PB0, 0, 0, 0),
DEF_TIM(TIM3, CH4, PB1, 0, 0, 0),
DEF_TIM(TIM3, CH1, PB4, 0, 0, 0),
DEF_TIM(TIM3, CH2, PB5, 0, 0, 0),
DEF_TIM(TIM4, CH1, PB6, 0, 0, 0),
DEF_TIM(TIM4, CH2, PB7, 0, 0, 0),
DEF_TIM(TIM4, CH3, PB8, 0, 0, 0),
DEF_TIM(TIM4, CH4, PB9, 0, 0, 0),
DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM12, CH1, PB14, 0, 0, 0),
DEF_TIM(TIM12, CH2, PB15, 0, 0, 0),
// Port C
DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM3, CH1, PC6, 0, 0, 0),
DEF_TIM(TIM3, CH2, PC7, 0, 0, 0),
DEF_TIM(TIM3, CH3, PC8, 0, 0, 0),
DEF_TIM(TIM3, CH4, PC9, 0, 0, 0),
DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM8, CH1, PC6, 0, 0, 0),
DEF_TIM(TIM8, CH2, PC7, 0, 0, 0),
DEF_TIM(TIM8, CH3, PC8, 0, 0, 0),
DEF_TIM(TIM8, CH4, PC9, 0, 0, 0),
// Port D
DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM4, CH1, PD12, 0, 0, 0),
DEF_TIM(TIM4, CH2, PD13, 0, 0, 0),
DEF_TIM(TIM4, CH3, PD14, 0, 0, 0),
DEF_TIM(TIM4, CH4, PD15, 0, 0, 0),
// Port E
DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM1, CH1N, PE8, 0, 0, 0),
DEF_TIM(TIM1, CH1, PE9, 0, 0, 0),
DEF_TIM(TIM1, CH2N, PE10, 0, 0, 0),
DEF_TIM(TIM1, CH2, PE11, 0, 0, 0),
DEF_TIM(TIM1, CH3N, PE12, 0, 0, 0),
DEF_TIM(TIM1, CH3, PE13, 0, 0, 0),
DEF_TIM(TIM1, CH4, PE14, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PE4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1, PE5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH2, PE6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM15, CH1N, PE4, 0, 0, 0),
DEF_TIM(TIM15, CH1, PE5, 0, 0, 0),
DEF_TIM(TIM15, CH2, PE6, 0, 0, 0),
// Port F
DEF_TIM(TIM16, CH1, PF6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1, PF7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM16, CH1, PF6, 0, 0, 0),
DEF_TIM(TIM17, CH1, PF7, 0, 0, 0),
DEF_TIM(TIM16, CH1N, PF8, 0, 0, 0),
DEF_TIM(TIM17, CH1N, PF9, 0, 0, 0),
DEF_TIM(TIM13, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM14, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TIM13, CH1N, PF8, 0, 0, 0),
DEF_TIM(TIM14, CH1N, PF9, 0, 0, 0),
// Port H
// Port H is not available for LPQFP-100 or 144 and TFBGA-100 package
// DEF_TIM(TIM12, CH1, PH6, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM5, CH1, PH10, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM8, CH1N, PH13, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, TIM_USE_ANY, 0, 0, 0),
// DEF_TIM(TIM12, CH1, PH6, 0, 0, 0),
// DEF_TIM(TIM12, CH2, PH9, 0, 0, 0),
// DEF_TIM(TIM5, CH1, PH10, 0, 0, 0),
// DEF_TIM(TIM5, CH2, PH11, 0, 0, 0),
// DEF_TIM(TIM5, CH3, PH12, 0, 0, 0),
// DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0),
// DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0),
// DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0),
};
#endif

16
src/main/drivers/timer.h
View file

@ -43,19 +43,6 @@ typedef uint32_t timCCER_t;
typedef uint32_t timSR_t;
typedef uint32_t timCNT_t;
typedef enum {
TIM_USE_ANY = 0x0,
TIM_USE_NONE = 0x0,
TIM_USE_PPM = 0x1,
TIM_USE_PWM = 0x2,
TIM_USE_MOTOR = 0x4,
TIM_USE_SERVO = 0x8,
TIM_USE_LED = 0x10,
TIM_USE_TRANSPONDER = 0x20,
TIM_USE_BEEPER = 0x40,
TIM_USE_CAMERA_CONTROL = 0x80,
} timerUsageFlag_e;
// use different types from capture and overflow - multiple overflow handlers are implemented as linked list
struct timerCCHandlerRec_s;
struct timerOvrHandlerRec_s;
@ -81,12 +68,10 @@ typedef struct timerHardware_s {
TIM_TypeDef *tim;
ioTag_t tag;
uint8_t channel;
timerUsageFlag_e usageFlags;
uint8_t output;
uint8_t alternateFunction;
#if defined(USE_TIMER_DMA)
#if defined(USE_DMA_SPEC)
dmaResource_t *dmaRefConfigured;
uint32_t dmaChannelConfigured;
@ -195,7 +180,6 @@ const resourceOwner_t *timerGetOwner(const timerHardware_t *timer);
const timerHardware_t *timerGetConfiguredByTag(ioTag_t ioTag);
const timerHardware_t *timerAllocate(ioTag_t ioTag, resourceOwner_e owner, uint8_t resourceIndex);
const timerHardware_t *timerGetByTagAndIndex(ioTag_t ioTag, unsigned timerIndex);
ioTag_t timerioTagGetByUsage(timerUsageFlag_e usageFlag, uint8_t index);
#if defined(USE_HAL_DRIVER)
TIM_HandleTypeDef* timerFindTimerHandle(TIM_TypeDef *tim);

6
src/main/drivers/timer_common.c
View file

@ -158,10 +158,4 @@ const timerHardware_t *timerAllocate(ioTag_t ioTag, resourceOwner_e owner, uint8
}
#endif
ioTag_t timerioTagGetByUsage(timerUsageFlag_e usageFlag, uint8_t index)
{
UNUSED(usageFlag);
UNUSED(index);
return IO_TAG_NONE;
}
#endif

14
src/test/unit/timer_definition_unittest.include/mock_enums.h
View file

@ -50,17 +50,3 @@ const char *const TEST_PIN_NAMES[TEST_PIN_SIZE] = {
"PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", "PH8", "PH9",
"PH10", "PH11", "PH12", "PH13", "PH14", "PH15",
};
enum TestTimUseEnum {
TIM_USE_ANY,
TIM_USE_BEEPER,
TIM_USE_CAMERA_CONTROL,
TIM_USE_LED,
TIM_USE_MOTOR,
TIM_USE_NONE,
TIM_USE_PPM,
TIM_USE_PWM,
TIM_USE_SERVO,
TIM_USE_TRANSPONDER,
TEST_TIM_USE_SIZE,
};